144 results about "Machine code" patented technology

A software package is received and unpacked into multiple components comprising plural functions. Each function is lifted from machine code into static single-assignment intermediate representation and tokenized to produce semantics-preserving embeddings. Intermediate-representation data-flow features are extracted, including detection of constant static variables on a stack, stack reaching definitions, uninitialized variables, and intra-procedural aliases. For each component, the embeddings and features are input to a machine-learning model trained on semantic properties derived from a corpus of software packages to generate a software supply chain risk level. Data characterizing the risk level is provided to a consuming application. When the risk level satisfies a remediation criterion, a remediation action is initiated, including generation of a source-code patch recommendation for an identified root-cause function, insertion of a runtime guard into the component, or issuance of a security advisory for distribution to a security operations dashboard.

A symmetric auto-compiler system (1) and method for high performance hardware optimized auto-parallelization of program code (3) executed by a multi-core or multi-processor parallel processing system (2) having a plurality of processing units (21) that simultaneously process instructions for data in the parallel processing system (2) by executing the program code (3). The automatic compiler system (1) converts serial source code (31) of program code (3) into parallel processing machine code (32) comprising a plurality of instructions executable by a plurality of processing units (21) of the parallel processing system (2) or controlling operation of the plurality of processing units (21).

Embodiments of the present application provide a method and device for compiling program code. The method for compiling program code may include: obtaining source code; and performing a compilation operation to obtain a first compilation result of the source code, where a first code segment in the source code is compiled into machine code in the first compilation result, a second code segment in the source code is compiled into bytecode in the first compilation result, and the first compilation result is configured to be deployed to a target environment. The proposed technical solutions may be conducive to ensuring performance at low storage resource utilization.

A system and method for universal static multi-transmit CPU design with a static pipeline for automatically parallelizing code is presented. A multi-core and / or multi-processor integrated circuit (2) has a plurality of processing units (21) and / or processing pipelines (53) that simultaneously process instructions for data by executing parallel processing machine code (32). The execution of the parallelized processing code (32) by the parallel processing multi-core and / or multi-processor integrated circuit (2) comprises the occurrence of a delay time (26), wherein the delay time is given by an idle time between the processing unit (21) returning the data after processing a specific instruction block of the processing code (32) for the data and receiving the data required by the processing unit (21) to execute a consecutive instruction block of the processing code (32). The parallel pipeline (53) comprises means for: (i) forwarding by providing a data forwarding from a MEM stage as an EX / MEM register to an EX stage as an ID / EX-stage register; (ii) exchanging by making the results of the Ex-ME-phase registers accessible by the Ex phase of a parallel pipeline (53) to provide a result exchange between the pipelines; and (iii) implementing branch pipeline refresh by providing control conflicts by refreshing only those pipelines (53) dependent on one pipeline (53) based on branch address computation conditions.

The invention discloses an error compensation method, device and equipment for a numerical control system and a storage medium, and relates to the technical field of machine tool precision control, and the error compensation method for the numerical control system comprises the steps: obtaining a machining code file and a compensation code file, and carrying out the matching detection of the machining code file and the compensation code file; after the matching detection is passed, analyzing the processing code file and the compensation code file to obtain a processing instruction and a compensation instruction; performing fusion processing on the processing instruction and the compensation instruction to generate an optimization interpolation instruction; and controlling the machine tool to move according to the optimized interpolation instruction. The error compensation efficiency of the numerical control system can be improved.

A method may comprise receiving a first neural network (NN) model including one or more functions; generating a second NN model in a form of directed acyclic graph (DAG) including one or more graph modules by converting the one or more functions; calculating one or more scale values by obtaining maximum and minimum values of parameters input to the one or more graph modules; updating the parameters based on the one or more scale values; and generating a third NN model, in a form of machine code executable on a particular neural processing unit, including the updated parameters.

The invention provides an RISC-V-oriented eBPF cycle vectorization compiling method and device, and the method comprises the steps: generating an RVV vector machine code, executing the parallel operation when a condition is satisfied, achieving the parallel processing of a single instruction and multiple data, carrying out the serial conversion of the time dimension of eBPF cycle into the parallel spatial dimension of an RVV vector, remarkably improving the processing throughput, and improving the compiling efficiency. And the task response time delay and the CPU occupancy rate are reduced. According to the RVV vector execution mode, a large number of repeated loop control instructions and memory read-write instructions can be reduced, the register overflow problem caused by eBPF scalar register resource shortage is relieved, the cache pressure and the branch prediction failure rate are reduced, and the energy efficiency ratio is increased. Meanwhile, an RVV vector machine code and a scalar fallback code are generated, a parallel priority and scalar bottom double execution path is formed, and it is ensured that under the conditions that a hardware environment is not supported, the data size does not reach a threshold value, vectorization verification fails or operation is abnormal, the scalar fallback code can be seamlessly switched to be executed.

Provided are systems, methods, and apparatuses for systems and methods of programming processes in processing in memory (PIM) systems. In one or more examples, the systems, devices, and methods include enabling, via a processor, a PIM manager for processing of PIM instructions, the PIM manager being located on a base die of a stacked memory module; enabling, via the PIM manager, a plurality of processing units of one or more memory dies of the stacked memory module for processing; compiling source code comprising the PIM instructions into machine code; loading, via PIM manager, the machine code into an allocation of memory of the stacked memory module; and executing, via the plurality of processing units, the PIM instructions based on loading the machine code into the memory of the stacked memory module.

The invention relates to the technical field of data processing, in particular to a GPU architecture conversion method and device. The method comprises the steps that assembly code input is received, ISA is analyzed into lexical units containing instruction elements according to input content, then detection of grammar rules and semantic logic is conducted on the lexical units based on grammar standards, and instruction objects carrying complete instruction attributes are generated; converting the instruction object into a corresponding LLVM function according to the attribute of the instruction object, generating an initial intermediate representation code, and finally compiling the optimized intermediate representation code into an executable machine code according to the target GPU hardware type. Through the embodiment of the invention, efficient conversion from the GPU assembly code to the multi-architecture machine code is realized, and the problem of performance loss caused by inaccurate grammar detection and insufficient optimization in traditional GPU development can be solved.

The invention provides a program language conversion method and device, computing equipment, a computer readable storage medium and a computer program product, and relates to the technical field of computer software, the method comprises the following steps: converting a variable definition in a to-be-converted program file written based on a first programming language into a variable definition about a second programming language; generating a target grammar structure tree according to the to-be-converted program file, wherein the target grammar structure tree is an abstract grammar tree which represents a grammar structure of the first programming language and carries semantics; based on the target grammar structure tree, generating a state machine code of a second programming language; and according to the variable definition related to the second programming language and the state machine code of the second programming language, generating a target program file related to the second programming language. According to the application, automatic conversion from the Basic program code to the Pascal program code can be realized.

A method (400) may include a processor core fetching (402) a packet of machine code instructions and then determining (404) whether a first machine code instruction of the packet corresponds to a coprocessor operation. In response to determining that the first machine code instruction corresponds to a coprocessor operation, the processor core may treat the other machine code instructions of the packet as no operations (NOOPs) and transmit (406) the machine code instructions of the packet to a coprocessor. The coprocessor may then decode and execute the machine code instructions. The method may further include the processor core keeping responsibility for load and store operations and, in the case of coprocessor operations, using (408, 410) registers of the coprocessor as source and destination for load and store operations.

This invention relates to the field of communication technology, specifically to a method for implementing a virtual serial port based on Hook technology. The method includes the following steps: replacing functions of the serial port operation API to open, set, and close the serial port and transmit data over the network; compiling this into a dynamic link library; using the dynamic link library to obtain the addresses of the serial port operation API functions CreateFileW, ReadFile, and WriteFile in the host computer process space; constructing a JMP jump instruction; writing it at the beginning of the target API function to redirect to a custom Hook function during the call; the custom Hook function calls the original API functions as needed; and canceling the Hook writes back the original machine code and restores memory attributes, resulting in a switchable monitoring function. This invention solves the problems of traditional serial port implementations, such as easy conflicts when multiple programs compete for usage, difficulty in flexibly monitoring and debugging serial communication, inability to conveniently simulate specific serial port scenarios, and poor scalability and compatibility with new systems or hardware platforms.

The invention discloses a code compiling device and method, and belongs to the technical field of computers. The device comprises a compiling module used for compiling a test program matched with a cost model for at least one section of candidate code, and the cost model is constructed by depending on the hardware performance of a target platform; the sending module is used for sending the test program to the target platform; the receiving module is used for receiving cost data obtained after the test program runs on the target platform, and the cost data is used for describing the running cost of at least one section of candidate code on the target platform; and the compiling module is also used for determining a target code from the at least one section of candidate code according to the cost data, and compiling the target code into a target machine code matched with the target platform. Therefore, the optimal machine code for the target platform is obtained, and user requirements are met.

The application is suitable for the technical field of computer security and artificial intelligence, and particularly relates to a binary code vulnerability detection method combining sparse attention and cross-modal interaction, comprising: S1, performing static analysis on target binary code to obtain hexadecimal machine code; S2, performing feature extraction to generate assembly modal feature representation and hexadecimal modal feature representation; S3, mapping the assembly modal feature representation and the hexadecimal modal feature representation to a shared representation space; S4, generating intra-modal local features and cross-modal global features by using an attention mechanism combining sparse attention and cross-modal interaction; S5, weighting and fusing the intra-modal local features and the cross-modal global features to generate multi-modal fusion representation; and S6, predicting a target vulnerability category through a decision layer based on the multi-modal fusion representation. By introducing the sparse attention mechanism, the application effectively reduces the computational complexity of long sequence processing, significantly improves the reasoning efficiency, and embodies high efficiency.

The application relates to a 3D printing deviation detection method, device and computer equipment. The method comprises the following steps: in a 3D printing process, current printing instruction data of a 3D printed part is acquired; after it is identified that the current printing layer is printed, the printing instruction data of the current printing layer is converted into target point cloud data; actual point cloud data of the current printing layer is acquired; the actual point cloud data is aligned with the target point cloud data, and deviation data of the current printing layer is obtained. In the method, an online detection system and a 3D printing system share a set of machining codes, target point cloud data of a current printing plane or curved surface can be generated in real time, and the real-time performance of 3D printing deviation detection is improved. The method is not affected by environmental light and temperature, does not need to construct a knowledge base or use a large amount of sample data for training, and can detect and record three-dimensional information of various printing defects including printed articles, and the accuracy and reliability of 3D printing deviation detection can be improved.

The invention discloses a gadget polishing process intelligent decision system applied to CAM industrial software. The gadget polishing process intelligent decision system mainly comprises the following steps: establishing a set of instance expressions which can be identified and used by a computer; establishing a small tool polishing instance database according to the instance expression; performing standardization and anomaly detection on the data in the instance library; establishing a process reasoning module for realizing static mapping from multiple input features to multiple output parameters; training a process reasoning module by using data in the instance library; a new small tool polishing process problem is imported into the process reasoning module; inputting the optimal prediction process parameters into industrial software with a CAM function; the industrial software generates a tool path and a machine code; the numerical control machine tool or the robot completes actual machining of the workpiece according to the machine code; and new data introduced by the new problem is recycled and classified into an instance library according to the instance expression requirements.

The invention provides a streaming processing method for real-time cleaning of agricultural product marketing data, and belongs to the technical field of big data processing.The method includes the steps that a field dependency directed graph is constructed, dependency intensity is quantified through mutual information, a dependency network is decomposed into weak coupling sub-graph sets through a minimum cut algorithm, and the weak coupling sub-graph sets are inserted into intermediate materialization nodes to achieve decoupling; performing Hamiltonian path inspired operator fusion optimization on each sub-graph to generate a super operator, converting the super operator into a machine code through a just-in-time compiler, establishing a multi-stage cache affinity scheduling mechanism and a dynamic watermark mechanism to process out-of-order data, and adopting a two-stage dynamic repartitioning strategy and a work stealing queue to cope with data skew; a hierarchical storage architecture is constructed, and capacity distribution is adjusted through a storage redundancy optimization function, so that the technical problem that the parallel processing capacity is limited due to a strong dependency relationship between fields in the agricultural product marketing data real-time cleaning process is solved.

A symmetric automatic compiler system (1) and method for high-performance, hardware-optimized automatic parallelization of program code (3) for execution by a multicore or multiprocessor parallel processing system (2) having multiple processing units (21) that simultaneously process instructions for data in a parallel processing system (2) by executing program code (3). The automatic compiler system (1) converts the sequential source code (31) of program code (3) into parallel processing machine code (32) which includes several instructions that can be executed by multiple processing units (21) of the parallel processing system (2) or that control the operation of multiple processing units (21).

The application relates to an automatic bidirectional conversion method and device for an instruction set in a heterogeneous multi-core project, computer equipment and a storage medium. The method comprises the following steps: obtaining an operation instruction to be converted; the operation instruction to be converted is an operation instruction supported by any one core in the heterogeneous multi-core project; using a compiler to compile the operation instruction to be converted to obtain machine code corresponding to the operation instruction; using a decoder to analyze the machine code to obtain an instruction type and an operand; scheduling the instruction type and the operand to an instruction set execution library different from the core where the operation instruction is located to perform matching to obtain machine code after instruction conversion; and performing disassembly on the machine code after instruction exchange to obtain converted instructions. The method can improve verification incentive efficiency.

The embodiments of the present specification provide a method for generating a bytecode, a method for generating a machine code, and a device. The method for generating a bytecode comprises: obtaining a target source code, and applying a first process to the target source code, the first process comprising: replacing a target statement used for an integer operation in the target source code with a preset objective function; on the basis of the target source code after the first processing, generating a target bytecode, the target bytecode comprising a bytecode instruction generated on the basis of a preset function, and the bytecode instruction instructing to perform the integer operation corresponding to the target statement by means of a preset machine instruction sequence, and to perform an overflow check for the integer operation.

A neural processing unit includes an internal memory including a plurality of memory units; a controller configured to control read and write operations of data in at least one of an input feature map domain, a weight domain, and an output feature map domain with respect to each of the plurality of memory units based on an operation schedule in a machine code in which a plurality of operation steps of an artificial neural network model are set.

A method may comprise receiving a first neural network (NN) model including one or more functions; generating a second NN model in a form of directed acyclic graph (DAG) including one or more graph modules by converting the one or more functions; calculating one or more scale values by obtaining maximum and minimum values of parameters input to the one or more graph modules; updating the parameters based on the one or more scale values; and generating a third NN model, in a form of machine code executable on a particular neural processing unit, including the updated parameters.

The application discloses a cluster data encryption and decryption method, device and system based on double trusted binding and decryption deadline control, relates to the technical field of information security, and comprises the following steps: collecting hardware characteristic information of a cluster terminal node, extracting a certain length of bytes as original machine code after processing; obtaining a dynamic key factor, extracting a specified length of bytes as a data key after processing; splicing the original machine code and certificate validity period information, generating certificate machine code after processing; splicing the original machine code and certificate validity period information, generating a machine envelope key after processing, performing symmetric encryption on the data key to obtain a machine key; generating a key certificate; and encrypting plaintext data by using the data key to obtain data ciphertext. The application introduces a multi-hardware characteristic fusion and multi-level key encryption system, and solves the problems of device identity impersonation, key leakage and uncontrollable data life cycle in a cluster environment.

The application provides a runtime suspension detection and positioning method and device for parallel programs, and applies to the technical field of large-scale computing. The method comprises the following steps: constructing a program counter value queue of each target execution unit at each sampling time; recording a stagnation program counter value of a target execution unit in a stagnation state; clustering the stagnation program counter value of the target execution unit to determine a suspended target execution unit; based on a machine instruction corresponding to the stagnation program counter value of the suspended target execution unit, obtaining source file and line number information corresponding to the stagnation program counter value through debugging information; and when the machine code corresponding to the stagnation program counter value of the suspended target execution unit is a call instruction, obtaining function call information. In this way, non-intrusive and low-load monitoring of parallel programs is realized, normal synchronization waiting and abnormal suspension processes are effectively distinguished, and problems are positioned to source code lines.

The application provides a certificate machine code correction method and a storage medium. The method comprises the following steps: cutting the machine code according to the certificate specification to obtain a plurality of identification objects; if one identification object has one missing character, the 731 weighting method is used to calculate and obtain the missing character according to the successfully recognized known character; if one identification object has two missing characters, the weight position and the at least two possible characters corresponding to each missing character are determined according to the identification result, wherein if the missing character is a check bit, the weight position corresponding to the missing character is set as a check bit identification value; and the 731 weighting method is used to determine each missing character according to the successfully recognized known character, the weight position and the at least two possible characters. The application can accurately and efficiently correct the missing characters when the complete machine code cannot be read.

This invention discloses a flexible job shop scheduling method and system based on a hybrid sandcat optimization algorithm. The method includes the following steps: S1, reading information from a standard format flexible job shop scheduling problem example, and storing the machine information, machine processing time information, and workpiece information in a list for classification; S2, randomly generating multiple feasible process codes and machine codes based on a two-stage coding rule as an initial population; S3, using the obtained initial population, setting the sandcat sensitivity, iteratively optimizing the process codes using a hybrid sine and cosine algorithm of the sandcat optimization algorithm, and updating the machine codes using a uniform crossover operator; S4, recording the minimum maximum completion time in the population after each iteration, and outputting the Gantt chart of the optimal solution obtained by the algorithm after the iteration. This invention solves the problem of inaccurate manual scheduling calculations in industrial production, which requires a large amount of human resources.

The embodiment of the invention provides an AI compiler, and relates to the field of communication. The AI compiler comprises a high-level processing layer which is used for converting a CUDA C Kernel code into an NVVM dialect and converting a non-CUDA C Kernel code into a non-NVVM dialect; the middle-end conversion layer is integrated with a first conversion module and a second conversion module, and is used for converting the NVVM dialect into an RISCV vector dialect or a matrix dialect based on the first conversion module and converting the non-NVVM dialect into an RISCV vector dialect or a matrix dialect based on the second conversion module; and the low-level processing layer is used for converting the RISCV vector dialect or the matrix dialect into a pure machine code file, so that the pure machine code file runs on an RISCV chip. Through the embodiment of the invention, the problem that the executable file translated by an AI compiler in the related technology can only run in a non-open source chip generally is solved, and the effect of enabling the generated executable file to run in an open source chip is further achieved.

The application discloses a kind of software protection system and method based on multidimensional coding, belong to software security technical field.System includes: multidimensional coding conversion module, multilayer obfuscated encryption module, runtime dynamic checking module, tamper self-destruction module, rule anchoring module.Multidimensional coding conversion module is converted into multinary coding with binary machine code;Multilayer obfuscated encryption module is based on preset obfuscated rule and carries out multilayer obfuscation to coding;Runtime dynamic checking module checks code integrity and running environment legality in real time;Tamper self-destruction module triggers self-destruction mechanism when detecting exception.The application fundamentally improves the strength of software anti-reverse engineering, and is suitable for the intellectual property protection of core software, algorithm, firmware.

An executable in a user-readable format that corresponds to a workflow function is received. The workflow function can be a stepwise process within a workflow. The executable is converted using one of natural language processing or a graph parsing algorithm and then an executable file is accessed. The executable file corresponds to the executable where the workflow function is associated with a task library function created by a machine-level language and stored at the executable file. The executable file is converted using the other of the natural language processing and the graph parsing algorithm. The converted executable file is then linked to a second user interface that is configured to present the workflow function in the user-readable format according to the stepwise process within the workflow.