298 results about "Machine code" patented technology

The embodiment of the invention provides a byte code generation method and device and a machine code generation method and device, and the byte code generation method comprises the steps that a target source code is obtained, first processing is applied to the target source code, and the first processing comprises the steps that a target statement used for integer operation in the target source code is replaced with a preset target function; according to the first processed target source code, a target byte code is generated, the target byte code comprises a byte code instruction generated according to a preset function, and the byte code instruction indicates that integer operation corresponding to the target statement is executed through a preset machine instruction sequence and overflow check for the integer operation is executed.

The invention discloses a database query execution method and device based on dynamic query compiling cache optimization, and belongs to the field of database management systems. Receiving a query statement input by a user and constructing an abstract syntax tree; generating a corresponding identifier according to the abstract syntax tree, searching a matched machine code, and loading and executing the matched machine code which can be reused to obtain an execution result; generating a corresponding executable plan tree for the query statement input by the user without finding the matched machine code or the query statement input by the user with the matched machine code incapable of being reused, generating and optimizing the machine code through dynamic compiling, obtaining the optimized machine code, and loading and executing the optimized machine code to obtain an execution result; and then an execution result is sent to the user, and machine codes in the cache are cleaned regularly. According to the method, whether the machine codes in the cache are multiplexed or not is accurately determined, so that unnecessary compilation overhead is reduced, and query execution efficiency is improved.

The invention provides a chip testing method and device, equipment, a storage medium and a program product. The method comprises the steps that operator codes, comprising multiple chip interface instructions, of a target operator are obtained, the target operator and a reference operator have the same calculation function, the chip interface instructions are used for achieving at least one hardware operation of a chip, and the hardware operations combining the multiple chip interface instructions are used for achieving the calculation function; analyzing the operator code to obtain a machine code file of the chip; test data are obtained, the test data and the machine code file are transmitted to chip simulation equipment, the chip simulation equipment is used for executing the machine code file on the test data, and a simulation calculation result of the target operator for the test data is obtained; obtaining a simulation calculation result from chip simulation equipment, and obtaining a reference calculation result of the reference operator for the test data; and generating a test result of the chip based on the simulation calculation result and the reference calculation result. According to the invention, the chip test progress can be accelerated.

A software package is received and unpacked into multiple components comprising plural functions. Each function is lifted from machine code into static single-assignment intermediate representation and tokenized to produce semantics-preserving embeddings. Intermediate-representation data-flow features are extracted, including detection of constant static variables on a stack, stack reaching definitions, uninitialized variables, and intra-procedural aliases. For each component, the embeddings and features are input to a machine-learning model trained on semantic properties derived from a corpus of software packages to generate a software supply chain risk level. Data characterizing the risk level is provided to a consuming application. When the risk level satisfies a remediation criterion, a remediation action is initiated, including generation of a source-code patch recommendation for an identified root-cause function, insertion of a runtime guard into the component, or issuance of a security advisory for distribution to a security operations dashboard.

The embodiment of the invention provides a code compiling method, electronic equipment and a storage medium. The code compiling method is used for compiling a code comprising at least one thread local storage variable, and comprises the following steps: in response to existence of a target thread local storage variable, allocating the at least one target thread local storage variable to a thread local memory based on an attribute of the at least one target thread local storage variable, obtaining a thread local memory address corresponding to each target thread local storage variable, wherein the target thread local storage variable is the thread local storage variable used by the first function; updating an intermediate representation corresponding to the code based on a thread local memory address corresponding to each target thread local storage variable; and generating a machine code corresponding to the code based on the updated intermediate representation. According to the code compiling method, thread local storage model support under a parallel computing architecture is provided, and the problem that traditional thread local storage implementation cannot be directly applied to a GPU architecture is solved.

A computer-based system and corresponding computer-implemented method process computation workloads to enable advanced functionality for data analytics. An execution resource is selected from a set of execution resources of a virtual machine (VM). The resource is for executing a VM instruction. The VM instruction is transformed into machine code for the resource selected. The code is executed via the resource selected. The executing furthers execution by the VM of a dataflow graph (DFG) including a compute node. The compute node has a set of VM instructions including the VM instruction. The DFG corresponds to a portion of a computation workload associated with a user data query. An output of the execution of the DFG represents a result of processing the workload and contributes to a response to the query. The system and method enable rapid and efficient retrieval and analysis of data in data storage systems, based on computation workloads.

A symmetric auto-compiler system (1) and method for high performance hardware optimized auto-parallelization of program code (3) executed by a multi-core or multi-processor parallel processing system (2) having a plurality of processing units (21) that simultaneously process instructions for data in the parallel processing system (2) by executing the program code (3). The automatic compiler system (1) converts serial source code (31) of program code (3) into parallel processing machine code (32) comprising a plurality of instructions executable by a plurality of processing units (21) of the parallel processing system (2) or controlling operation of the plurality of processing units (21).

The invention discloses a license authorization management method for a software platform, which comprises the following steps of: storing files or data by adopting a multi-way tree type storage structure, granting a user permission of a corresponding node level according to different nodes of the multi-way tree type storage structure, generating a unique machine code according to the user permission and server hardware information, and storing the unique machine code into a server; performing digital signature on the machine code to generate a legal authorization file; finally, when the user accesses the corresponding node, performing authorization file verification, and judging whether the authorization file verification is passed or not; and the effect of browsing, viewing or modifying hierarchical management aiming at users with different permissions is realized.

A system includes a substrate on which a first memory, a neural processing unit (NPU) including a plurality of processing elements (PEs) with multiplier-accumulator circuits, a controller, and a second memory, and a central processing unit (CPU) are disposed. The CPU may be configured to execute a universal compiler to perform a conversion for a particular neural network model into a machine code executable by the NPU and store the machine code in the first memory or the second memory. When the particular neural network model, generated by one among a plurality of machine learning frameworks that are incompatible with each other, is received and stored in the first memory, the universal compiler may perform the conversion based on mapping information indicating mapping between elements of machine learning frameworks and functions or operations executable by the CPU or NPU.

The invention relates to a deep learning model reasoning method and device, computer equipment and a storage medium. The method comprises the following steps: calling an inference framework matched with a domestic accelerator, and performing compilation optimization, parallel optimization, memory hierarchical optimization and deep fusion of calculation acceleration components on a deep learning model to obtain a target optimization model; compiling the target optimization model into an executable machine code of the domestic accelerator; and loading the executable machine code on the domestic accelerator, and executing a data reasoning process of the executable machine code on to-be-reasoned data to obtain a model reasoning result. By adopting the method, the problem that an existing general reasoning framework is difficult to directly adapt to the domestic accelerator can be solved, the calculation potential of the domestic accelerator is completely released, and the reasoning efficiency and the resource utilization rate are remarkably improved.

Embodiments of the present application provide a method and device for compiling program code. The method for compiling program code may include: obtaining source code; and performing a compilation operation to obtain a first compilation result of the source code, where a first code segment in the source code is compiled into machine code in the first compilation result, a second code segment in the source code is compiled into bytecode in the first compilation result, and the first compilation result is configured to be deployed to a target environment. The proposed technical solutions may be conducive to ensuring performance at low storage resource utilization.

The present disclosure relates to improving the performance of evaluating path expressions on hierarchical data objects represented by binary encoded documents. An abstract syntax tree (AST) representing a path expression may be generated, wherein the AST comprises one or more syntax nodes implementing one or more respective execution steps of an evaluation of the path expression, and the path expression is included in a query to a database management system (DBMS). The AST may be modified based at least in part on profiling information and compiled into machine code. Using the machine code, the path expression may be executed on a binary-encoded hierarchical document.

The embodiment of the invention provides a code compiling method, electronic equipment and a storage medium. The code compiling method is used for compiling a code comprising at least one thread local storage variable, and comprises the following steps: acquiring a record of the thread local storage variable used by each first function in the code, and transmitting the record to a driver, enabling the driver to distribute each thread local storage variable to a thread local memory according to the record during operation; a machine code corresponding to the code is generated according to the intermediate representation corresponding to the code, the machine code comprises a loading instruction, and the loading instruction is used for obtaining a thread local memory address corresponding to each thread local storage variable based on the allocation result of the driver when being executed. According to the code compiling method, a mechanism of dynamically allocating the address space during operation is adopted, so that the waste of the local memory space of the thread is avoided, and the utilization rate of the local memory space of the thread is improved.

Systems and methods are provided that incorporate a compiler configured to convert interpreted language code (e.g., Python) into native machine code. According to some embodiments, the system generates the native machine code into a format that is consistent with known infrastructure. The native machine code can be converted into a format based on a low level virtual machine “LLVM” infrastructure. In various embodiments, the system enables a compiler framework that improves execution of code for interpreted languages. According to one embodiment, the system can be tailored for execution on specific processors, for example, a graphics processing unit (“GPU”) that is optimized for highly parallel computations.

A method for executing a debugging process of a control program of an automation system includes receiving a first machine code source code relation and a first source code identity, by a development system for executing the debugging process, in a receiving step; comparing the first source code identity with a second source code identity of a second source code version executed on the development system, in a source code comparing step; generating a version identity based on the comparison of the source code identities, in an identity generating step; determining a second machine code source code relation based on the first machine code source code relation and the version identity, in a relation determining step; and executing the debugging process of the machine code stored on the controller based on the second source code version, using the second machine code source code relation, in a debugging step.

A system and method for universal static multi-transmit CPU design with a static pipeline for automatically parallelizing code is presented. A multi-core and / or multi-processor integrated circuit (2) has a plurality of processing units (21) and / or processing pipelines (53) that simultaneously process instructions for data by executing parallel processing machine code (32). The execution of the parallelized processing code (32) by the parallel processing multi-core and / or multi-processor integrated circuit (2) comprises the occurrence of a delay time (26), wherein the delay time is given by an idle time between the processing unit (21) returning the data after processing a specific instruction block of the processing code (32) for the data and receiving the data required by the processing unit (21) to execute a consecutive instruction block of the processing code (32). The parallel pipeline (53) comprises means for: (i) forwarding by providing a data forwarding from a MEM stage as an EX / MEM register to an EX stage as an ID / EX-stage register; (ii) exchanging by making the results of the Ex-ME-phase registers accessible by the Ex phase of a parallel pipeline (53) to provide a result exchange between the pipelines; and (iii) implementing branch pipeline refresh by providing control conflicts by refreshing only those pipelines (53) dependent on one pipeline (53) based on branch address computation conditions.

The embodiment of the invention discloses an application program running method and device, a terminal, a storage medium and a product, and belongs to the technical field of software. Comprising the steps that in the process of downloading a target application program, a target configuration file of the target application program is determined based on a configuration file of at least one application program contained in a first terminal, the target configuration file comprises a machine code of a hotspot function corresponding to hotspot operation, and the hotspot operation refers to operation with the execution frequency exceeding the preset frequency; the hotspot function is used for processing a hotspot operation, and a machine code of the hotspot function is obtained by compiling a byte code of the hotspot function; storing the target configuration file into a storage space corresponding to a storage path of the target application program; when the hotspot operation is executed based on the target application program, obtaining a machine code of a hotspot function from a target configuration file in the storage space; and executing the machine code of the hotspot function.

The invention discloses an error compensation method, device and equipment for a numerical control system and a storage medium, and relates to the technical field of machine tool precision control, and the error compensation method for the numerical control system comprises the steps: obtaining a machining code file and a compensation code file, and carrying out the matching detection of the machining code file and the compensation code file; after the matching detection is passed, analyzing the processing code file and the compensation code file to obtain a processing instruction and a compensation instruction; performing fusion processing on the processing instruction and the compensation instruction to generate an optimization interpolation instruction; and controlling the machine tool to move according to the optimized interpolation instruction. The error compensation efficiency of the numerical control system can be improved.

A method may comprise receiving a first neural network (NN) model including one or more functions; generating a second NN model in a form of directed acyclic graph (DAG) including one or more graph modules by converting the one or more functions; calculating one or more scale values by obtaining maximum and minimum values of parameters input to the one or more graph modules; updating the parameters based on the one or more scale values; and generating a third NN model, in a form of machine code executable on a particular neural processing unit, including the updated parameters.

Apparatuses, systems, and techniques of using one or more circuits (e.g., of a network interface) to obtain assembly code for one or more machine code segments loaded and / or injected into a process, and determine whether the assembly code is likely to perform at least one unauthorized task.

The invention discloses an industrial control system configuration cloud compiling method and system, and relates to the technical field of cloud computing cross.The method comprises the steps that a logic flow graph is traversed in a depth-first mode, the occurrence frequency of an instruction operation code is counted, and an information density degree evaluation value of a program code is calculated; based on the information intensive evaluation value, analyzing the distribution characteristics of the occurrence frequency of the operation code type and the weight of the operation code, and combining with an instruction entropy threshold comparison result, identifying a high-frequency redundant instruction operation code, compressing and combining the high-frequency redundant instruction operation code, optimizing a conditional jump structure of a logic flow graph, and generating an intermediate optimization code unit; and based on the intermediate optimization code unit, carrying out topological dependency analysis and implementing local increment compiling verification to generate an executable machine code. According to the method, the information intensity evaluation value of the program code is calculated, the high-frequency redundant operation code is accurately recognized, semantic-level compression and combination are carried out, and a simple and reliable control program code is generated under the condition of maintaining industrial hard real-time constraint.

The invention provides an RISC-V-oriented eBPF cycle vectorization compiling method and device, and the method comprises the steps: generating an RVV vector machine code, executing the parallel operation when a condition is satisfied, achieving the parallel processing of a single instruction and multiple data, carrying out the serial conversion of the time dimension of eBPF cycle into the parallel spatial dimension of an RVV vector, remarkably improving the processing throughput, and improving the compiling efficiency. And the task response time delay and the CPU occupancy rate are reduced. According to the RVV vector execution mode, a large number of repeated loop control instructions and memory read-write instructions can be reduced, the register overflow problem caused by eBPF scalar register resource shortage is relieved, the cache pressure and the branch prediction failure rate are reduced, and the energy efficiency ratio is increased. Meanwhile, an RVV vector machine code and a scalar fallback code are generated, a parallel priority and scalar bottom double execution path is formed, and it is ensured that under the conditions that a hardware environment is not supported, the data size does not reach a threshold value, vectorization verification fails or operation is abnormal, the scalar fallback code can be seamlessly switched to be executed.

The invention relates to a verification and test integrated platform for a probe processor, and belongs to the technical field of processor verification and test. A probe processor adopts a self-defined probe instruction and a special probe operator unit, and a traditional verification and test mode is difficult to consider the requirements of module-level verification and system-level test. The UVM verification system, the test system and the management module are integrated, and unified management of verification and test is achieved. The UVM verification system is based on a UVM architecture, a virtual interface is associated with a to-be-tested unit (such as a probe operator, GPIO, UART and the like) of a probe processor through a forced binding mechanism, and module-level verification is achieved. The test system is responsible for compiling test codes into machine codes and loading the machine codes to the probe processor by starting the read-only memory, and system-level test is executed by the probe processor. And the management module adopts an automatic script to realize intelligent switching between verification and test modes, so that the probe processor is suitable for different test scenes, the test efficiency is improved, and the environmental redundancy is reduced. According to the method, the reusability of the test case is improved, the test consistency is ensured, the resource utilization rate is optimized, the automation degree and efficiency of verification are improved, and the method is suitable for efficient verification and test of probe processors and similar architecture chips.

Provided are systems, methods, and apparatuses for systems and methods of programming processes in processing in memory (PIM) systems. In one or more examples, the systems, devices, and methods include enabling, via a processor, a PIM manager for processing of PIM instructions, the PIM manager being located on a base die of a stacked memory module; enabling, via the PIM manager, a plurality of processing units of one or more memory dies of the stacked memory module for processing; compiling source code comprising the PIM instructions into machine code; loading, via PIM manager, the machine code into an allocation of memory of the stacked memory module; and executing, via the plurality of processing units, the PIM instructions based on loading the machine code into the memory of the stacked memory module.

The invention discloses a dynamic generation and verification system for a bidirectional authentication software license based on a national cryptographic algorithm, and the system comprises a hash unit which is used for carrying out the hash operation of a machine code to obtain a machine code hash value, and carrying out the verification of the hash code and the original data of the machine code; the encryption unit is used for encrypting the client information at the client to obtain client encrypted information; according to the random number generation and confusion unit, client software obtains a random number through a random number seed and a random number generator, and a software service provider side carries out confusion operation on the random number through a confusion algorithm to obtain a random number confusion value; and the verification unit is used for carrying out reverse obfuscation algorithm on the random number obfuscation value by the client, carrying out comparison verification on the random number obfuscation value and a random numerical value transmitted to a software service provider, reading the machine code, calculating hash, and carrying out hash verification on the machine code abstract in the license. The method has the advantages that the safety performance is high, the anti-attack capability is improved, and the flexibility of software offline authorization is improved.

The invention relates to the technical field of data processing, in particular to a GPU architecture conversion method and device. The method comprises the steps that assembly code input is received, ISA is analyzed into lexical units containing instruction elements according to input content, then detection of grammar rules and semantic logic is conducted on the lexical units based on grammar standards, and instruction objects carrying complete instruction attributes are generated; converting the instruction object into a corresponding LLVM function according to the attribute of the instruction object, generating an initial intermediate representation code, and finally compiling the optimized intermediate representation code into an executable machine code according to the target GPU hardware type. Through the embodiment of the invention, efficient conversion from the GPU assembly code to the multi-architecture machine code is realized, and the problem of performance loss caused by inaccurate grammar detection and insufficient optimization in traditional GPU development can be solved.

The invention relates to the technical field of embedded software development, and discloses a finite-state machine automatic generation method and system and related equipment, and the method comprises the steps: obtaining a table path corresponding to a preset table; wherein the configuration generated by the state machine code framework filled by the user is stored in the preset table; on the basis of the table path, configuration in a preset table is captured through a python script, and a state machine code framework is generated; and storing the state machine code framework in a preset storage path specified by a user, so that the user can check the state machine code framework. According to the method and the device, the state machine code framework is automatically generated through the script written by the python language, so that the complexity of personally writing the code by a developer is avoided, and the development efficiency is improved.

The invention relates to the technical field of laser processing, in particular to a processing code overtravel detection method of a laser cutting numerical control system, which mainly comprises the following steps: receiving a processing code generated by CAM software, the processing code comprising processing length information of a pipe, a part and a contour; a stroke limiting detection macro-program is embedded in the machining code, and the stroke detection macro-program is used for conducting logic processing according to the starting point coordinate, the machining length and the limiting coordinate of the machining code and judging whether an over-stroke condition exists or not; when the machining codes are executed, stroke detection is conducted on the machining paths of the whole pipe, the single part and the single cutting contour tool path in sequence through the stroke detection macro program, and a detection result is obtained; and adjusting execution logic of the processing code according to the detection result and preset logic. According to the method, overtravel detection is carried out on the machining codes in advance, the problems of cutting interruption and material waste caused by insufficient travel are avoided, and the cutting efficiency is improved.

The invention provides a program language conversion method and device, computing equipment, a computer readable storage medium and a computer program product, and relates to the technical field of computer software, the method comprises the following steps: converting a variable definition in a to-be-converted program file written based on a first programming language into a variable definition about a second programming language; generating a target grammar structure tree according to the to-be-converted program file, wherein the target grammar structure tree is an abstract grammar tree which represents a grammar structure of the first programming language and carries semantics; based on the target grammar structure tree, generating a state machine code of a second programming language; and according to the variable definition related to the second programming language and the state machine code of the second programming language, generating a target program file related to the second programming language. According to the application, automatic conversion from the Basic program code to the Pascal program code can be realized.

The invention relates to the technical field of optical machining, in particular to a method for automatically generating a complex curved surface machining numerical control program. Comprising the following steps: collecting related information of the complex curved surface, including information of the complex curved surface, process parameters when the complex curved surface is processed and program information of a numerical control machine tool when the complex curved surface is processed; collecting a plurality of groups of data in the above steps to obtain a complex curved surface information data set, taking the process information data set as an input data set, and obtaining a numerical control program data set as an output data set; constructing a transfer learning network; the input data set is input and trained, and a complex curved surface machining code prediction model is obtained; and according to the requirement of a complex curved surface machining task, information of the complex curved surface and technological parameters when the complex curved surface is machined are obtained and input into the complex curved surface machining code prediction model, a machine tool numerical control code can be obtained, and efficient machining of the complex curved surface is achieved. The method has the advantages of being short in calculation time, improving polishing precision and efficiency and enhancing model adaptability.