231 results about "Machine code" patented technology

The invention provides a chip testing method and device, equipment, a storage medium and a program product. The method comprises the steps that operator codes, comprising multiple chip interface instructions, of a target operator are obtained, the target operator and a reference operator have the same calculation function, the chip interface instructions are used for achieving at least one hardware operation of a chip, and the hardware operations combining the multiple chip interface instructions are used for achieving the calculation function; analyzing the operator code to obtain a machine code file of the chip; test data are obtained, the test data and the machine code file are transmitted to chip simulation equipment, the chip simulation equipment is used for executing the machine code file on the test data, and a simulation calculation result of the target operator for the test data is obtained; obtaining a simulation calculation result from chip simulation equipment, and obtaining a reference calculation result of the reference operator for the test data; and generating a test result of the chip based on the simulation calculation result and the reference calculation result. According to the invention, the chip test progress can be accelerated.

A software package is received and unpacked into multiple components comprising plural functions. Each function is lifted from machine code into static single-assignment intermediate representation and tokenized to produce semantics-preserving embeddings. Intermediate-representation data-flow features are extracted, including detection of constant static variables on a stack, stack reaching definitions, uninitialized variables, and intra-procedural aliases. For each component, the embeddings and features are input to a machine-learning model trained on semantic properties derived from a corpus of software packages to generate a software supply chain risk level. Data characterizing the risk level is provided to a consuming application. When the risk level satisfies a remediation criterion, a remediation action is initiated, including generation of a source-code patch recommendation for an identified root-cause function, insertion of a runtime guard into the component, or issuance of a security advisory for distribution to a security operations dashboard.

A symmetric auto-compiler system (1) and method for high performance hardware optimized auto-parallelization of program code (3) executed by a multi-core or multi-processor parallel processing system (2) having a plurality of processing units (21) that simultaneously process instructions for data in the parallel processing system (2) by executing the program code (3). The automatic compiler system (1) converts serial source code (31) of program code (3) into parallel processing machine code (32) comprising a plurality of instructions executable by a plurality of processing units (21) of the parallel processing system (2) or controlling operation of the plurality of processing units (21).

A system includes a substrate on which a first memory, a neural processing unit (NPU) including a plurality of processing elements (PEs) with multiplier-accumulator circuits, a controller, and a second memory, and a central processing unit (CPU) are disposed. The CPU may be configured to execute a universal compiler to perform a conversion for a particular neural network model into a machine code executable by the NPU and store the machine code in the first memory or the second memory. When the particular neural network model, generated by one among a plurality of machine learning frameworks that are incompatible with each other, is received and stored in the first memory, the universal compiler may perform the conversion based on mapping information indicating mapping between elements of machine learning frameworks and functions or operations executable by the CPU or NPU.

The invention relates to a deep learning model reasoning method and device, computer equipment and a storage medium. The method comprises the following steps: calling an inference framework matched with a domestic accelerator, and performing compilation optimization, parallel optimization, memory hierarchical optimization and deep fusion of calculation acceleration components on a deep learning model to obtain a target optimization model; compiling the target optimization model into an executable machine code of the domestic accelerator; and loading the executable machine code on the domestic accelerator, and executing a data reasoning process of the executable machine code on to-be-reasoned data to obtain a model reasoning result. By adopting the method, the problem that an existing general reasoning framework is difficult to directly adapt to the domestic accelerator can be solved, the calculation potential of the domestic accelerator is completely released, and the reasoning efficiency and the resource utilization rate are remarkably improved.

Embodiments of the present application provide a method and device for compiling program code. The method for compiling program code may include: obtaining source code; and performing a compilation operation to obtain a first compilation result of the source code, where a first code segment in the source code is compiled into machine code in the first compilation result, a second code segment in the source code is compiled into bytecode in the first compilation result, and the first compilation result is configured to be deployed to a target environment. The proposed technical solutions may be conducive to ensuring performance at low storage resource utilization.

Systems and methods are provided that incorporate a compiler configured to convert interpreted language code (e.g., Python) into native machine code. According to some embodiments, the system generates the native machine code into a format that is consistent with known infrastructure. The native machine code can be converted into a format based on a low level virtual machine “LLVM” infrastructure. In various embodiments, the system enables a compiler framework that improves execution of code for interpreted languages. According to one embodiment, the system can be tailored for execution on specific processors, for example, a graphics processing unit (“GPU”) that is optimized for highly parallel computations.

A method for executing a debugging process of a control program of an automation system includes receiving a first machine code source code relation and a first source code identity, by a development system for executing the debugging process, in a receiving step; comparing the first source code identity with a second source code identity of a second source code version executed on the development system, in a source code comparing step; generating a version identity based on the comparison of the source code identities, in an identity generating step; determining a second machine code source code relation based on the first machine code source code relation and the version identity, in a relation determining step; and executing the debugging process of the machine code stored on the controller based on the second source code version, using the second machine code source code relation, in a debugging step.

A system and method for universal static multi-transmit CPU design with a static pipeline for automatically parallelizing code is presented. A multi-core and / or multi-processor integrated circuit (2) has a plurality of processing units (21) and / or processing pipelines (53) that simultaneously process instructions for data by executing parallel processing machine code (32). The execution of the parallelized processing code (32) by the parallel processing multi-core and / or multi-processor integrated circuit (2) comprises the occurrence of a delay time (26), wherein the delay time is given by an idle time between the processing unit (21) returning the data after processing a specific instruction block of the processing code (32) for the data and receiving the data required by the processing unit (21) to execute a consecutive instruction block of the processing code (32). The parallel pipeline (53) comprises means for: (i) forwarding by providing a data forwarding from a MEM stage as an EX / MEM register to an EX stage as an ID / EX-stage register; (ii) exchanging by making the results of the Ex-ME-phase registers accessible by the Ex phase of a parallel pipeline (53) to provide a result exchange between the pipelines; and (iii) implementing branch pipeline refresh by providing control conflicts by refreshing only those pipelines (53) dependent on one pipeline (53) based on branch address computation conditions.

The invention discloses an error compensation method, device and equipment for a numerical control system and a storage medium, and relates to the technical field of machine tool precision control, and the error compensation method for the numerical control system comprises the steps: obtaining a machining code file and a compensation code file, and carrying out the matching detection of the machining code file and the compensation code file; after the matching detection is passed, analyzing the processing code file and the compensation code file to obtain a processing instruction and a compensation instruction; performing fusion processing on the processing instruction and the compensation instruction to generate an optimization interpolation instruction; and controlling the machine tool to move according to the optimized interpolation instruction. The error compensation efficiency of the numerical control system can be improved.

A method may comprise receiving a first neural network (NN) model including one or more functions; generating a second NN model in a form of directed acyclic graph (DAG) including one or more graph modules by converting the one or more functions; calculating one or more scale values by obtaining maximum and minimum values of parameters input to the one or more graph modules; updating the parameters based on the one or more scale values; and generating a third NN model, in a form of machine code executable on a particular neural processing unit, including the updated parameters.

Apparatuses, systems, and techniques of using one or more circuits (e.g., of a network interface) to obtain assembly code for one or more machine code segments loaded and / or injected into a process, and determine whether the assembly code is likely to perform at least one unauthorized task.

The invention discloses an industrial control system configuration cloud compiling method and system, and relates to the technical field of cloud computing cross.The method comprises the steps that a logic flow graph is traversed in a depth-first mode, the occurrence frequency of an instruction operation code is counted, and an information density degree evaluation value of a program code is calculated; based on the information intensive evaluation value, analyzing the distribution characteristics of the occurrence frequency of the operation code type and the weight of the operation code, and combining with an instruction entropy threshold comparison result, identifying a high-frequency redundant instruction operation code, compressing and combining the high-frequency redundant instruction operation code, optimizing a conditional jump structure of a logic flow graph, and generating an intermediate optimization code unit; and based on the intermediate optimization code unit, carrying out topological dependency analysis and implementing local increment compiling verification to generate an executable machine code. According to the method, the information intensity evaluation value of the program code is calculated, the high-frequency redundant operation code is accurately recognized, semantic-level compression and combination are carried out, and a simple and reliable control program code is generated under the condition of maintaining industrial hard real-time constraint.

The invention provides an RISC-V-oriented eBPF cycle vectorization compiling method and device, and the method comprises the steps: generating an RVV vector machine code, executing the parallel operation when a condition is satisfied, achieving the parallel processing of a single instruction and multiple data, carrying out the serial conversion of the time dimension of eBPF cycle into the parallel spatial dimension of an RVV vector, remarkably improving the processing throughput, and improving the compiling efficiency. And the task response time delay and the CPU occupancy rate are reduced. According to the RVV vector execution mode, a large number of repeated loop control instructions and memory read-write instructions can be reduced, the register overflow problem caused by eBPF scalar register resource shortage is relieved, the cache pressure and the branch prediction failure rate are reduced, and the energy efficiency ratio is increased. Meanwhile, an RVV vector machine code and a scalar fallback code are generated, a parallel priority and scalar bottom double execution path is formed, and it is ensured that under the conditions that a hardware environment is not supported, the data size does not reach a threshold value, vectorization verification fails or operation is abnormal, the scalar fallback code can be seamlessly switched to be executed.

The invention relates to a verification and test integrated platform for a probe processor, and belongs to the technical field of processor verification and test. A probe processor adopts a self-defined probe instruction and a special probe operator unit, and a traditional verification and test mode is difficult to consider the requirements of module-level verification and system-level test. The UVM verification system, the test system and the management module are integrated, and unified management of verification and test is achieved. The UVM verification system is based on a UVM architecture, a virtual interface is associated with a to-be-tested unit (such as a probe operator, GPIO, UART and the like) of a probe processor through a forced binding mechanism, and module-level verification is achieved. The test system is responsible for compiling test codes into machine codes and loading the machine codes to the probe processor by starting the read-only memory, and system-level test is executed by the probe processor. And the management module adopts an automatic script to realize intelligent switching between verification and test modes, so that the probe processor is suitable for different test scenes, the test efficiency is improved, and the environmental redundancy is reduced. According to the method, the reusability of the test case is improved, the test consistency is ensured, the resource utilization rate is optimized, the automation degree and efficiency of verification are improved, and the method is suitable for efficient verification and test of probe processors and similar architecture chips.

Provided are systems, methods, and apparatuses for systems and methods of programming processes in processing in memory (PIM) systems. In one or more examples, the systems, devices, and methods include enabling, via a processor, a PIM manager for processing of PIM instructions, the PIM manager being located on a base die of a stacked memory module; enabling, via the PIM manager, a plurality of processing units of one or more memory dies of the stacked memory module for processing; compiling source code comprising the PIM instructions into machine code; loading, via PIM manager, the machine code into an allocation of memory of the stacked memory module; and executing, via the plurality of processing units, the PIM instructions based on loading the machine code into the memory of the stacked memory module.

The invention relates to the technical field of data processing, in particular to a GPU architecture conversion method and device. The method comprises the steps that assembly code input is received, ISA is analyzed into lexical units containing instruction elements according to input content, then detection of grammar rules and semantic logic is conducted on the lexical units based on grammar standards, and instruction objects carrying complete instruction attributes are generated; converting the instruction object into a corresponding LLVM function according to the attribute of the instruction object, generating an initial intermediate representation code, and finally compiling the optimized intermediate representation code into an executable machine code according to the target GPU hardware type. Through the embodiment of the invention, efficient conversion from the GPU assembly code to the multi-architecture machine code is realized, and the problem of performance loss caused by inaccurate grammar detection and insufficient optimization in traditional GPU development can be solved.

The invention relates to the technical field of embedded software development, and discloses a finite-state machine automatic generation method and system and related equipment, and the method comprises the steps: obtaining a table path corresponding to a preset table; wherein the configuration generated by the state machine code framework filled by the user is stored in the preset table; on the basis of the table path, configuration in a preset table is captured through a python script, and a state machine code framework is generated; and storing the state machine code framework in a preset storage path specified by a user, so that the user can check the state machine code framework. According to the method and the device, the state machine code framework is automatically generated through the script written by the python language, so that the complexity of personally writing the code by a developer is avoided, and the development efficiency is improved.

The invention provides a program language conversion method and device, computing equipment, a computer readable storage medium and a computer program product, and relates to the technical field of computer software, the method comprises the following steps: converting a variable definition in a to-be-converted program file written based on a first programming language into a variable definition about a second programming language; generating a target grammar structure tree according to the to-be-converted program file, wherein the target grammar structure tree is an abstract grammar tree which represents a grammar structure of the first programming language and carries semantics; based on the target grammar structure tree, generating a state machine code of a second programming language; and according to the variable definition related to the second programming language and the state machine code of the second programming language, generating a target program file related to the second programming language. According to the application, automatic conversion from the Basic program code to the Pascal program code can be realized.

The invention relates to the technical field of national cryptographic algorithm acceleration, and discloses a national cryptographic algorithm acceleration system based on a Numba just-in-time compiling technology. The numerical calculation mode reconstruction module is used for performing numerical calculation mode reconstruction on SM2 elliptic curve scalar multiplication, SM3 message extension round function, SM4 nonlinear transformation and ZUC flow generation logic contained in the national cryptographic algorithm core calculation module by utilizing an LLVM compiling chain of Numba, and converting an interpretively executed Python code into an optimized machine code adaptive to hardware; key function compiling acceleration is achieved through a (at) njit decorator, hot spot operation is dynamically recognized through compiling scheduling, and a differential instruction optimization strategy is loaded; the platform shows multiple technical advantages: on the development efficiency level, by presetting a standardized acceleration module library and an automatic compiling tool chain, the integration complexity of a national cryptographic algorithm is greatly reduced; in the aspect of operation performance, the compilation optimization depth is better than that of a general interpreter acceleration scheme; in the aspect of safety controllability, the mathematical theory basis of the national cryptographic algorithm is completely reserved, and hidden risks possibly introduced by black box type hardware acceleration are avoided.

The present disclosure belongs to the field of software engineering technology, and specifically relates to a method, storage medium, and smart terminal for adding code to an executable file. The method comprises: obtaining and parsing the structure of a target Mach‑O file in the memory of an iOS system or a macOS system; migrating all segments after the code segment in the structure to a preset blank area at the end of the file to free up continuous memory space, expanding the code segment to include the continuous memory space, inserting machine code into the continuous memory space based on a code insertion tool that does not require recompilation, wherein the code segment refers to the __TEXT segment; and automatically correcting the address offset caused by segment movement. The present disclosure provides a method for adding code to an Apple system Mach‑O file that complies with Apple's listing review policy and has more flexible functional expansion.

A method (400) may include a processor core fetching (402) a packet of machine code instructions and then determining (404) whether a first machine code instruction of the packet corresponds to a coprocessor operation. In response to determining that the first machine code instruction corresponds to a coprocessor operation, the processor core may treat the other machine code instructions of the packet as no operations (NOOPs) and transmit (406) the machine code instructions of the packet to a coprocessor. The coprocessor may then decode and execute the machine code instructions. The method may further include the processor core keeping responsibility for load and store operations and, in the case of coprocessor operations, using (408, 410) registers of the coprocessor as source and destination for load and store operations.

This invention relates to the field of communication technology, specifically to a method for implementing a virtual serial port based on Hook technology. The method includes the following steps: replacing functions of the serial port operation API to open, set, and close the serial port and transmit data over the network; compiling this into a dynamic link library; using the dynamic link library to obtain the addresses of the serial port operation API functions CreateFileW, ReadFile, and WriteFile in the host computer process space; constructing a JMP jump instruction; writing it at the beginning of the target API function to redirect to a custom Hook function during the call; the custom Hook function calls the original API functions as needed; and canceling the Hook writes back the original machine code and restores memory attributes, resulting in a switchable monitoring function. This invention solves the problems of traditional serial port implementations, such as easy conflicts when multiple programs compete for usage, difficulty in flexibly monitoring and debugging serial communication, inability to conveniently simulate specific serial port scenarios, and poor scalability and compatibility with new systems or hardware platforms.

The invention discloses a code compiling device and method, and belongs to the technical field of computers. The device comprises a compiling module used for compiling a test program matched with a cost model for at least one section of candidate code, and the cost model is constructed by depending on the hardware performance of a target platform; the sending module is used for sending the test program to the target platform; the receiving module is used for receiving cost data obtained after the test program runs on the target platform, and the cost data is used for describing the running cost of at least one section of candidate code on the target platform; and the compiling module is also used for determining a target code from the at least one section of candidate code according to the cost data, and compiling the target code into a target machine code matched with the target platform. Therefore, the optimal machine code for the target platform is obtained, and user requirements are met.

The application is suitable for the technical field of computer security and artificial intelligence, and particularly relates to a binary code vulnerability detection method combining sparse attention and cross-modal interaction, comprising: S1, performing static analysis on target binary code to obtain hexadecimal machine code; S2, performing feature extraction to generate assembly modal feature representation and hexadecimal modal feature representation; S3, mapping the assembly modal feature representation and the hexadecimal modal feature representation to a shared representation space; S4, generating intra-modal local features and cross-modal global features by using an attention mechanism combining sparse attention and cross-modal interaction; S5, weighting and fusing the intra-modal local features and the cross-modal global features to generate multi-modal fusion representation; and S6, predicting a target vulnerability category through a decision layer based on the multi-modal fusion representation. By introducing the sparse attention mechanism, the application effectively reduces the computational complexity of long sequence processing, significantly improves the reasoning efficiency, and embodies high efficiency.

The application relates to a 3D printing deviation detection method, device and computer equipment. The method comprises the following steps: in a 3D printing process, current printing instruction data of a 3D printed part is acquired; after it is identified that the current printing layer is printed, the printing instruction data of the current printing layer is converted into target point cloud data; actual point cloud data of the current printing layer is acquired; the actual point cloud data is aligned with the target point cloud data, and deviation data of the current printing layer is obtained. In the method, an online detection system and a 3D printing system share a set of machining codes, target point cloud data of a current printing plane or curved surface can be generated in real time, and the real-time performance of 3D printing deviation detection is improved. The method is not affected by environmental light and temperature, does not need to construct a knowledge base or use a large amount of sample data for training, and can detect and record three-dimensional information of various printing defects including printed articles, and the accuracy and reliability of 3D printing deviation detection can be improved.

The invention discloses a gadget polishing process intelligent decision system applied to CAM industrial software. The gadget polishing process intelligent decision system mainly comprises the following steps: establishing a set of instance expressions which can be identified and used by a computer; establishing a small tool polishing instance database according to the instance expression; performing standardization and anomaly detection on the data in the instance library; establishing a process reasoning module for realizing static mapping from multiple input features to multiple output parameters; training a process reasoning module by using data in the instance library; a new small tool polishing process problem is imported into the process reasoning module; inputting the optimal prediction process parameters into industrial software with a CAM function; the industrial software generates a tool path and a machine code; the numerical control machine tool or the robot completes actual machining of the workpiece according to the machine code; and new data introduced by the new problem is recycled and classified into an instance library according to the instance expression requirements.

The invention provides a streaming processing method for real-time cleaning of agricultural product marketing data, and belongs to the technical field of big data processing.The method includes the steps that a field dependency directed graph is constructed, dependency intensity is quantified through mutual information, a dependency network is decomposed into weak coupling sub-graph sets through a minimum cut algorithm, and the weak coupling sub-graph sets are inserted into intermediate materialization nodes to achieve decoupling; performing Hamiltonian path inspired operator fusion optimization on each sub-graph to generate a super operator, converting the super operator into a machine code through a just-in-time compiler, establishing a multi-stage cache affinity scheduling mechanism and a dynamic watermark mechanism to process out-of-order data, and adopting a two-stage dynamic repartitioning strategy and a work stealing queue to cope with data skew; a hierarchical storage architecture is constructed, and capacity distribution is adjusted through a storage redundancy optimization function, so that the technical problem that the parallel processing capacity is limited due to a strong dependency relationship between fields in the agricultural product marketing data real-time cleaning process is solved.

The invention provides a binary instrumentation method for an LL / SC lock instruction. The binary instrumentation method comprises the steps that S1, a DBI tool is prepared in advance and started; s2, loading an LL / SC atomic operation instruction sequence and distributing a corresponding memory; s3, decoding and translating a machine code corresponding to the LL / SC atomic operation instruction sequence by the DBI tool, and converting the machine code into an IR intermediate expression; s4, shadow memory instrumentation is carried out based on IR intermediate expression; and S5, converting the IR intermediate expression after instrumentation into a target machine code, and running in a simulation environment of a DBI tool to obtain execution information of the LL / SC atomic operation instruction sequence. According to the method, correct translation and code instrumentation can be carried out on the multi-thread application containing the LL / SC, correct translation of the LL / SC instruction pair in the binary instrumentation framework is ensured, and correctness and atomicity of modification of the translated instruction to the sharing state in the competition state are ensured.

The invention discloses a code processing device, a processor, a code processing method and a decoding method, and belongs to the technical field of computers. The code processing device comprises an input module used for obtaining a code file, and the code file comprises machine codes of a plurality of instructions; the processing module is used for determining a target instruction from the multiple instructions; and the processor is used for compressing the machine code of the target instruction into a compressed code, storing the compressed code into the storage space and generating a machine instruction, and the machine instruction is used for reading the compressed code from the storage space and restoring the compressed code into the machine code of the target instruction. In this way, the code area in the code file is reduced, and meanwhile stable operation of the instruction is guaranteed.