The utility model provides a functional detection and
verification platform used for an RISC-V framework. The RISC-V processor comprises an RISC-V processor, an HPCA connector and an HPCB connector are arranged on the RISC-V processor, the HPCA connector is connected with a
FLASH memory and an SRAM memory, and the HPCB connector is connected with a
CAN bus, a QSPI interface, an NAND memory, an SPACE WIRE
bus, an IIC
bus, a UART
transmitter, a PWM, a 1553B
bus and an SPI interface. The utility model relates to the technical field of
integrated circuit design
verification platforms.