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3 results about "RISC-V" patented technology

RISC-V (pronounced "risk-five") is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. The project began in 2010 at the University of California, Berkeley, but many contributors are volunteers not affiliated with the university.

Audio noise reduction accelerator system and method based on RISC v custom instruction set expansion

The present invention claims protection for an audio noise reduction accelerator system and method based on the expansion of RISC v custom instruction set, which belongs to the field of integrated circuit technology, and mainly includes: E203_CORE, NICE_CORE, NICE_Interface, E203_SOC, audio codec WM8731 module, and audio noise reduction FxLMS algorithm. Among them, E203_CORE is connected to NICE_CORE through NICE_Interface, E203_CORE, NICE_CORE and related peripheral ports together form E203_SOC, E203_SOC is connected to the audio codec WM8731 module, and the audio noise reduction FxLMS algorithm is downloaded to the RISC v processor core through software programming for operation. The innovation point is that compared with the processor of ARM instruction set architecture, the processor using RISC v custom instruction set can accelerate the specific operation part of the audio noise reduction FxLMS algorithm; the present invention can further optimize the problems of area, power consumption, granularity, etc., while improving the flexibility and feasibility of the algorithm.
Owner:SHENZHEN JUSHENG TECHNOLOGY CO LTD

Functional detection and verification platform for RISC-V architecture

The utility model provides a functional detection and verification platform used for an RISC-V framework. The RISC-V processor comprises an RISC-V processor, an HPCA connector and an HPCB connector are arranged on the RISC-V processor, the HPCA connector is connected with a FLASH memory and an SRAM memory, and the HPCB connector is connected with a CAN bus, a QSPI interface, an NAND memory, an SPACE WIRE bus, an IIC bus, a UART transmitter, a PWM, a 1553B bus and an SPI interface. The utility model relates to the technical field of integrated circuit design verification platforms.
Owner:ZHUHAI ORBITA AEROSPACE SCI TECH CO LTD