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Rapid IO interface suitable for RISC-V architecture kernel

A RISC-V, fast technology, applied in the direction of instrumentation, electrical digital data processing, etc., can solve complex problems

Inactive Publication Date: 2019-07-30
芯来智融半导体科技(上海)有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For the control of these devices, it is more complicated to use the traditional serial port or parallel port. Therefore, a "general programmable I / O port" is usually provided on the embedded microprocessor, that is, the GPIO port

Method used

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  • Rapid IO interface suitable for RISC-V architecture kernel
  • Rapid IO interface suitable for RISC-V architecture kernel
  • Rapid IO interface suitable for RISC-V architecture kernel

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Embodiment 1

[0038] The FIO interface design of the present invention includes the following interface signals, including fio_icb_cmd_valid, fio_icb_cmd_addr, fio_icb_cmd_read, fio_icb_cmd_dmode, fio_icb_cmd_mmode, fio_icb_cmd_wdata, fio_icb_cmd_wmask, fio_icb_rsp_rdata, fio_icb_rsp_err, as shown in Table 1.

[0039] Table 1. FIO interface design signal list and description table of the present invention

[0040]

[0041] in:

[0042] The fio_icb_cmd_valid (FIO access request command valid control signal), when the signal is 1, means that the current access of the FIO interface is a valid access, and when the signal is 0, it means that the current access of the FIO interface is an invalid access .

[0043] The fio_icb_cmd_addr (FIO access request command address signal), this signal indicates the address value of the current FIO access.

[0044] The fio_icb_cmd_read (FIO access request command read and write control signal), when the signal is 1, means that the current access of the F...

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Abstract

The invention discloses a rapid IO interface suitable for an RISC-V architecture kernel. The rapid IO interface comprises a request channel and a feedback channel, and the request channel is used forthe processor kernel to request data writing from peripheral equipment through the fast IO interface; the feedback channel is used for the fast IO interface to return read data to the processor kernel, and the fast IO interface is directly connected with the processor; and the quick IO interface is connected with the GPIO port and the peripheral equipment. The rapid IO interface is directly connected with the processor without transferring through a bus, so that the processor can quickly and efficiently access the peripheral interface.

Description

technical field [0001] The present invention relates to the present invention relates to low power consumption core coprocessor interface technology, especially relates to a kind of fast IO interface suitable for RISC-V framework core. Background technique [0002] In embedded systems, it is often necessary to control many external devices or circuits with simple structures. Some of these devices need to be controlled by the CPU, and some require the CPU to provide input signals. Moreover, many devices or circuits only require two states of on and off, such as the on and off of LEDs. For the control of these devices, it is more complicated to use the traditional serial port or parallel port. Therefore, a "general programmable I / O port", that is, a GPIO port, is usually provided on the embedded microprocessor. [0003] A GPIO port requires at least two registers, a "general IO port control register" for control, and a "general I / O port data register" for storing data. Each ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/10G06F13/12G06F13/42
CPCG06F13/102G06F13/126G06F13/4221
Inventor 周在新
Owner 芯来智融半导体科技(上海)有限公司
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