An I2C-based RISC-V controller debugging method and device

A technology of RISC-V and debugging method, which is applied in the computer field, can solve the problems of direct monitoring and debugging of RISC-V controller chip BMC system, debugging RISC-V controller chip, etc., and achieve the effect of reducing the difficulty of debugging and speeding up the debugging speed
CN109684147AInactive Publication Date: 2019-04-26ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
ZHENGZHOU YUNHAI INFORMATION TECH CO LTD
Publication Date
2019-04-26
Estimated Expiration
Not applicable · inactive patent

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Abstract

The invention discloses an I2C-based RISC-V controller debugging method and device. The I2C-based RISC-V controller debugging method comprises the steps in the RISC-V controller, the I2C debug moduleis used to obtain the instr value from the instruction fetch module; the instr value is transferred from the I2C debug module of the RISC-V controller to the IMC controller of the BMC through the I2Cbus; in the BMC, The I2C controller is used to notify the ARM processor to read the instr value and send it to the terminal; the terminal parses the instr value into an instruction and displays the instruction for the user to debug. The technical solution of the invention can monitor and debug different RISC-V controller chips or different types of RISC-V controller chips, which reduces debuggingdifficulty and speeds up debugging.
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Description

technical field

[0001] The present invention relates to the field of computers, and more specifically, to an I2C-based RISC-V controller debugging method and device. Background technique

[0002] I2C (internal integrated circuit) is widely used in the server field to control and monitor information such as sensors and fans in the server. The interface is simple, easy to operate, and easy to use. It is an indispensable interface in the BMC management system. RISC-V (the fifth generation of reduced instruction set computer, Reduced Instruction Set Computer V) is an open instruction set architecture based on the principle of reduced instruction set computing. It has the characteristics of complete open source, simple structure, easy transplantation, and modular design. However, many RISC-V controller chips in the X86 server in the prior art cannot be directly monitored and debugged through the BMC system, and can only be debugged at the design stage and require a dedicated debu...

Claims

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