Exception and interruption processing system and method based on RISC-V architecture

A RISC-V, exception handling technology, applied in the direction of response errors, etc., can solve problems such as the system cannot be recovered, and achieve the effect of speeding up the response speed

Active Publication Date: 2019-06-25
AMOLOGIC (SHANGHAI) CO LTD
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Problems solved by technology

Therefore, in the RISC-V architecture, there is a problem that...

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  • Exception and interruption processing system and method based on RISC-V architecture
  • Exception and interruption processing system and method based on RISC-V architecture
  • Exception and interruption processing system and method based on RISC-V architecture

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no. 1 example

[0087] Specifically, such as image 3 As shown, the first embodiment of the interrupt processing method includes the following steps:

[0088] Step S10, when the core of the processor responds to the interrupt request, update the current state of the processor and store the return address of the interrupt handler of the processor, obtain the base address of the interrupt vector of the processor, and start executing the interrupt processing corresponding to the interrupt request model;

[0089] Step S11, after executing the interrupt processing mode corresponding to the interrupt request, update the state of the interrupt processing and the current state of the processor, restore the instruction address of the processor from the return address of the interrupt processing program of the processor, and exit the corresponding interrupt request interrupt handling mode.

[0090] Further, as Figure 4 As shown, the first embodiment of the interrupt processing method includes the f...

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Abstract

The invention relates to the technical field of low-power-consumption kernel interrupt processing, in particular to an exception and interruption processing system and method based on an RISC-V architecture. The exception and interruption processing system comprises a mode register, an exception vector base address register, a state register, an exception cause register, an exception return address register, an interruption vector base address register, an interruption state register and an interruption return address register. Beneficial effects are as follows: the feed additive is A mode register is added in a kernel of a processor, and the interrupt vector base address register, the interrupt state register and the interrupt return address register are used for separately processing theinterrupt processing mode and the exception processing mode of the processor, so that a program of the processor can exit from the exception processing mode and the interrupt processing mode when theexception nesting interrupt exists, and the system can recover when the exception nesting interrupt exists.

Description

technical field [0001] The invention relates to the technical field of low-power-consumption kernel interrupt processing, in particular to an exception and interrupt processing system and method based on RISC-V architecture. Background technique [0002] Interrupt mechanism (Interrupt), that is, the processor core is suddenly interrupted by other requests in the process of sequentially executing the program instruction flow and suspends the execution of the current program, and turns to process other things. After it finishes processing other things, then Return to the point where the previous program was interrupted and continue to execute the previous program instruction flow. Among them, the "other request" that interrupts the processor's execution of the program instruction flow is called an interrupt request (Interrupt Request), and the source of the interrupt request is called an interrupt source (Interrupt Source). Usually, the interrupt source is mainly from periphe...

Claims

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Application Information

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IPC IPC(8): G06F11/07
Inventor 吴俊顾冲李青
Owner AMOLOGIC (SHANGHAI) CO LTD
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