An instruction downloading method and device for an RISC-V processor

Abstract

The invention discloses an instruction downloading method and device for an RISC-V processor based on a field programmable gate array FPGA development board, and the method comprises the steps: receiving a test instruction through an IO interface, and storing the test instruction in an instruction memory; Generating a switching instruction, and switching the instruction memory into a to-be-testedreduced instruction set calculation RISC-V processor for operation; Controlling the to-be-tested RISC-V processor to be reset, reading the test instruction in the instruction memory and operating thetest instruction. The method does not rely on the jtag interface and nand-flash but carries out instruction download through a common IO interface and an instruction memory, thereby improving universality of the test of the RISC-V processor. The invention further discloses an FPGA development board based on the method.

Description

technical field

[0001] The invention relates to the technical field of processor debugging, in particular to a RISC-V processor instruction downloading method and a device thereof. The invention also relates to an FPGA development board. Background technique

[0002] In the CPU (Central Processing Unit, central processing unit) design, you can design the CPU you need based on the open RISC-V architecture, that is, the ultra-low power consumption RISC-V (reduced instruction set computing) processor (Hummingbird E203). In the process of designing and debugging the processor, it is necessary to burn the processor to the development board, and download the upper-layer test instructions through the interface of the development board for testing and debugging. Because FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) has the advantages of fast speed, high efficiency, flexibility and stability, and high integration, FPGA development boards are usually used for pr...

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