An instruction downloading method and device for an RISC-V processor

A RISC-V, processor instruction technology, applied in electrical digital data processing, instrumentation, computing and other directions, can solve problems such as poor versatility

Active Publication Date: 2019-04-26
GUANGDONG INSPUR BIG DATA RES CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, in this solution, the command download must rely on the nand-flash and jtag interface, so there are restrictions on the specifications of the F

Method used

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  • An instruction downloading method and device for an RISC-V processor
  • An instruction downloading method and device for an RISC-V processor
  • An instruction downloading method and device for an RISC-V processor

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Embodiment Construction

[0047] The core of the present invention is to provide a RISC-V processor instruction download method and its device, which does not depend on the jtag interface and nand-flash, but performs instruction download through the general IO interface and instruction memory, which improves the RISC-V processing The versatility of device test; Another core of the present invention is to provide a kind of FPGA development board based on said method.

[0048] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill...

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Abstract

The invention discloses an instruction downloading method and device for an RISC-V processor based on a field programmable gate array FPGA development board, and the method comprises the steps: receiving a test instruction through an IO interface, and storing the test instruction in an instruction memory; Generating a switching instruction, and switching the instruction memory into a to-be-testedreduced instruction set calculation RISC-V processor for operation; Controlling the to-be-tested RISC-V processor to be reset, reading the test instruction in the instruction memory and operating thetest instruction. The method does not rely on the jtag interface and nand-flash but carries out instruction download through a common IO interface and an instruction memory, thereby improving universality of the test of the RISC-V processor. The invention further discloses an FPGA development board based on the method.

Description

technical field [0001] The invention relates to the technical field of processor debugging, in particular to a RISC-V processor instruction downloading method and a device thereof. The invention also relates to an FPGA development board. Background technique [0002] In the CPU (Central Processing Unit, central processing unit) design, you can design the CPU you need based on the open RISC-V architecture, that is, the ultra-low power consumption RISC-V (reduced instruction set computing) processor (Hummingbird E203). In the process of designing and debugging the processor, it is necessary to burn the processor to the development board, and download the upper-layer test instructions through the interface of the development board for testing and debugging. Because FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) has the advantages of fast speed, high efficiency, flexibility and stability, and high integration, FPGA development boards are usually used for pr...

Claims

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Application Information

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IPC IPC(8): G06F11/263
CPCG06F11/263Y02D10/00
Inventor 王凯
Owner GUANGDONG INSPUR BIG DATA RES CO LTD
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