68 results about "Buffer overflow" patented technology

The invention discloses a prospective preprocessing method and system in six-axis mechanical motion automatic control, particularly relates to the field of six-axis mechanical motion automatic control, and is used for solving the problem of insufficient track prediction and control precision in a load sudden change scene. The inertia tensor is updated in real time in combination with dual-channel Kalman filtering, dynamic inertia data are accessed, and the sensitivity of trajectory prediction to load change is improved; double-domain feature extraction of time-domain thermal stress density and frequency-domain energy dispersion is adopted, acceleration pulse layout is dynamically optimized by using a complementary integral mechanism, and the overload risk of a driver is reduced; meanwhile, the instruction dispatcher avoids cache overflow through advanced rhythm regulation and control, and continuity of instruction streams is guaranteed; the inertia model is continuously refreshed through closed-loop feedback, and synchronous evolution of inertia change and trajectory prediction is achieved; the overload shutdown risk caused by inertia lag of six-axis mechanical motion is reduced, and the adaptive capacity of the prospective preprocessing method in a dynamic complex operation environment is enhanced.

The invention belongs to the technical field of network protocol stacks, and particularly relates to a method and a device for constructing an embedded network protocol stack based on Rust, common memory errors can be avoided by using the network protocol stack compiled by the Rust, a memory management mechanism of the Rust comprises an automatic recovery mechanism and an ownership system, the memory which is not used any more can be automatically released, and the reliability of the network protocol stack is improved. The common memory security problems of memory leakage, buffer overflow, repeated release and the like of the existing network protocol stack in an embedded system are solved, and the stability and the performance of the system are improved. The performance of the network protocol stack is optimized while the security of the memory is ensured, and the protocol stack is suitable for various embedded devices, especially in environments requiring high-reliability and efficient memory management. According to the network protocol stack, the memory security problem existing in a common network protocol stack is solved, and meanwhile, the effect which cannot be achieved by rewriting the network protocol stack only by simply using the Rust is achieved.

The invention provides a buffer overflow vulnerability decision judgment method and system based on an extension value flow graph, and relates to the technical field of computers, and the method comprises the steps: analyzing an abstract syntax tree corresponding to a to-be-detected program, and determining the extension value flow graph corresponding to the to-be-detected program; all nodes in the extension value flow graph are traversed, and vulnerability nodes corresponding to the to-be-detected program are determined; the vulnerable node is a node which may have a buffer overflow vulnerability; determining a constraint condition corresponding to the vulnerability node; the constraint condition is used for ensuring that the vulnerable node does not generate buffer overflow; and determining a buffer overflow vulnerability detection result of the to-be-detected program based on a solving result of the constraint condition. According to the method and the system provided by the invention, the detection precision and the detection efficiency of the buffer overflow vulnerability are improved.

The present disclosure relates to a 5G or 6G communication system for supporting higher data transmission rates. The present invention relates to a method by which a UE reports a new UE capability parameter to a base station in order for the UE to reduce a layer 2 (L2) buffer size required for preventing packet loss due to buffer overflow.

The invention discloses a method and a system for protecting privacy of source codes in memory error detection, belongs to the technical field of computer software security, and particularly relates to a technology for protecting confidentiality of the source codes in a third-party memory error analysis process of software. According to the method, a debugging information minimization processing system DIREDUCER is constructed, a selective deletion and type minimization technology is utilized, on the premise that complete source codes are not exposed, necessary debugging information used for memory error detection is effectively reserved, and dual guarantee of source code privacy and memory error detection effects is achieved. According to the method, the debugging information in the non-stripping binary file is compressed to be within 10% of the original volume, and the recognition capability of an analysis tool on the problems such as memory leak, buffer overflow and overhanging pointers is not remarkably reduced. Experimental results show that the method has good adaptability and expandability in actual deployment, is suitable for various debugging tools and binary analysis frameworks, and has wide application prospects and practical values.

Apparatus and methods for improving throughput and reliability in a wireless network. In one embodiment, the apparatus and methods provide mechanisms for wireless user device buffer management that mitigate buffer overflow within the device due to overscheduling, such as from different networks with which the device is connected simultaneously. In one variant, a 3GPP-based signaling architecture from wireless device to the multiple networks is provided to enable user device-controlled management buffer overflow. In another variant, potentially buffer-demanding (e.g., HARQ) process management and prioritization rules are defined to avoid buffer overflow. In other variant, buffer size computation is provided considering the number of networks to which the wireless user device can connect.

The invention relates to a serial port instruction intelligent processing method and device based on multi-frame cache and a storage medium. The method comprises the steps that a system is initialized; starting serial port interruption to receive a serial port AT instruction; the received instruction is analyzed; after analysis is completed, the AT instructions are further classified; after instructions are classified and stored in corresponding queues, the system adopts a priority scheduling algorithm to determine which instruction is processed preferentially; and the system executes corresponding operation according to the specific content of the instruction. According to the method, a multi-level cache pool technology is adopted, a virtual cache queue is constructed on a software layer, the equivalent cache capacity is expanded, and the situation that a hardware buffer overflows or instructions are lost due to insufficient process processing capacity is avoided; a priority instruction scheduling algorithm is introduced, instruction grades are dynamically divided, key instructions are ensured to be processed preferentially, and the problem that a traditional single-frame mode cannot respond in time when the MCU is in a high load state is solved; and meanwhile, enhanced frame identification of the protocol is realized, and the problem of insufficient error correction capability of a traditional mode is solved.

A device for receiving media data includes a memory configured to store media data of a media presentation and one or more processors implemented in circuitry and configured to retrieve a service description including data including one or more playback preferences for the media presentation, the playback preferences including a desired end-to-end latency; retrieve the media data of the media presentation via a network streaming protocol; and present the retrieved media data according to the one or more playback preferences and to achieve the desired end-to-end latency. For example, the playback preferences may specify acceleration or deceleration of playback rates in order to achieve the desired end-to-end latency. Thus, the device may accelerate playback if a buffer is filling too quickly, or decelerate playback if the buffer is emptying too quickly, to prevent buffer overflow or underflow and thereby avoid playback interruptions without changing the latency.

Techniques relating to buffers are disclosed. A first buffer may be for storing a number of elements for processing. Disclosed techniques include providing a second buffer for storing elements for adding to the first buffer, and adding an obtained element to the second buffer when the number of elements in the first buffer is greater than a first threshold. These techniques can prevent overrun of the first buffer while allowing the obtained element to be added to a buffer.

An apparatus is provided comprising a buffer in direct memory access communication with a network interface to receive data packets comprising data payload portions containing data in a stream of time-synchronous media, a buffer to temporarily store a plurality of time-synchronous media records extracted from the data payload portions, wherein respective ones of the plurality of time-synchronous media records is associated with a respective media channel, a data router circuit to read one of the plurality of time-synchronous media records from the buffer route that time-synchronous media record to a media interface, and a buffer monitor circuit to monitor a ratio of stored records and read records and to trigger a processor interrupt in the event of a buffer underflow or buffer overflow.

The invention discloses a serial port communication method and system based on a multi-core chip system and a readable storage medium. According to the method, one CPU core is reserved, and the specified serial port interrupt processing is only executed in the reserved CPU core, so that the serial port interrupt processing is not influenced by other processes and operation system scheduling, the serial port interrupt processing capability of the multi-core chip system is effectively improved, the throughput of serial port data is increased, and the system performance is improved. The problem of data loss caused by untimely serial port interruption processing is reduced; the appointed serial port data processing task is only executed in the reserved CPU core, so that the delay of serial port data processing due to system scheduling is avoided, the real-time capability of serial port data processing of the multi-core chip system is improved, the real-time processing capability of the system to the serial port is improved, and in the serial port data processing task, the real-time processing capability of the system to the serial port is improved. And the receiving and transmitting priority of the serial port is set to be the highest priority, and the receiving and transmitting of the data are processed preferentially, so that the received data is prevented from being lost due to overflow of the receiving buffer.

The invention relates to a software and hardware combined fine-grained memory protection mechanism, which realizes high-speed mapping from a physical address to a fine-grained permission label by integrating a metadata search unit and a metadata conversion lookup buffer on a critical path of a processor loading / storage unit. An operating system maintains a multi-level fine-grained permission metadata table in a main memory, and the minimum memory protection granularity is refined to a 64-byte sub-page level. When a processor executes a memory access instruction, address conversion and permission verification are completed in parallel, an access type and a permission label are compared in real time within 1-2 clock periods, and when permission conflicts are detected, high-priority abnormity is triggered immediately, and illegal addresses and fault types are reported accurately. The method supports instruction set extension, buffer overflow protection, multi-level metadata management and user mode and kernel mode differentiated authority control, reduces the influence on the performance of the processor while improving the security of the memory, and is suitable for a computing system with high security and high performance.

Embodiments of the present disclosure provide a data discarding method, a communication device, a communication system, a storage medium, and a program product. The method is executed by a terminal, and the method comprises: discarding a first data packet among at least one packet data convergence protocol (PDCP) data packet, wherein the first data packet is a PDCP data packet that can be first discarded among the at least one PDCP data packet. In the technical solution provided by the embodiments of the present disclosure, a terminal discards a first data packet that can be first discarded among at least one PDCP data packet, thereby reducing the number of PDCP data packets to be processed or transmitted, thus effectively alleviating buffer overflow of the terminal, and also ensuring timely processing and transmission of PDCP data packets among the at least one PDCP data packet other than the first data packet.

A method and system track memory allocation and release activities to detect memory leak, buffer overflow, and release type mismatch errors in a computing system. The memory tracker computes the necessary size of the allocated memory block and calls operating system provided functions to allocate and release raw memory blocks. Raw memory blocks are formatted into allocated memory blocks. An indexed data structure stores the allocated memory blocks. The user memory address is used as the index key value. The memory blocks are removed from the indexed data structure when the programs release the memory. The memory blocks remaining in the indexed data structure are considered memory leaks when the memory tracker terminates. The memory tracker adds bytes to the end of memory blocks for the integrity check and detects possible buffer overflow errors. Memory allocation type is added in the allocated memory blocks for release type mismatch errors.

The application provides a per-port flow control method, medium and equipment suitable for BCube topology, which comprises a per-port queue allocation strategy, a dynamic flow control mechanism and a queue grouping strategy. In the design of the switch port queue, each outgoing port of the switch has an independent queue corresponding to the downstream switch port, thereby reducing the congestion problem caused by burst traffic. In the design of the host port queue, the host is allocated a special queue according to the traffic characteristics, thereby avoiding the head-of-line blocking when different types of traffic contend for resources. The dynamic flow control mechanism dynamically adjusts the sending rate of the upstream node queue according to the buffer state of the downstream switch, thereby preventing the buffer overflow; the queue type of the congested port is monitored in real time, a pause or resume signal is generated, different types of traffic are managed separately, and the transmission efficiency is improved. In the queue grouping strategy, the switch port queue is divided into different priorities, the propagation of the congestion signal is reduced, the circular dependency is avoided, and the network is prevented from stalling.

The invention provides a memory access security checking method for a GPU compiler. The memory access security checking method comprises the following steps: converting a GPU code into a high-level IR instruction; according to metadata information in the high-level IR instruction, extracting a boundary allocated by each memory, and converting the high-level IR instruction into a low-level IR instruction; and based on a range analysis method of a transfer function, in the rear end of the compiler, performing data stream analysis on the low-level IR instruction, calculating a symbolized address range of each memory access, and checking the security of each memory access based on the symbolized range of each memory access and the boundary of each memory allocation. The method for performing memory access security check on the low-level IR language level in the GPU compiler is used for checking the problems of memory cross-border access or buffer overflow and the like which possibly occur after the rear end of the compiler is subjected to multiple optimizations, does not depend on a specific hardware architecture or a specific IR language, and has certain universality.

A hardware framework for cyber-deception operations provides flexibility in formulating counterattacks and leverages hardware support for efficiency. Hardware-assisted deception primitives are provided at kernel crossing boundaries to privileged system features that propel the security defenses to dynamically manipulate the malware execution and present a deceptive view of the system state to the attackers. Malware may be in the form of various attack vectors including ransomware, infostealers, buffer overflow, and side-channels.

Aspects of the invention include an operating system executing on a processor receiving a write request from a program to write data to memory. The write request includes a virtual memory address and data. It is determined that the virtual memory address is not assigned to a physical memory address. Based on the determination, the unassigned virtual memory address is assigned to a physical memory address in an overflow memory. The data is written to the physical memory address in the overflow memory, and an indication of a successful write of the data is returned to the program. Future requests by the program to access the virtual memory address are directed to the physical memory address in the overflow memory.

The present application belongs to the field of security monitoring digital signal processing technology, and relates to a kind of hierarchical security area invasion event intelligent identification method, comprising: obtaining the security weight score of the region to be identified;Sampling video signal and generating stream data message composed of binary bit stream;Compare adjacent data frames to extract feature disturbance offset;Real-time monitoring of the instantaneous load rate of data bus;Coupling weight score and feature disturbance offset, introduce instantaneous load rate to calculate the task scheduling priority of stream data message;When the task scheduling priority exceeds the dynamic adaptive threshold, drive the central processor to start the fast processing channel based on level 1 cache prefetching, the present application dynamically adjusts the data access threshold through the load feedback mechanism, effectively eliminates the risk of buffer overflow, and enhances the high-risk data priority analysis capability of the system under extreme overload working conditions.

One or more aspects of the present disclosure relate to controlling input / output consumption to prevent port congestion in storage networks. A storage array detects initiator port speeds and maps them to storage ports using masking information. The system tracks aggregate IO consumption across connected storage ports, including in NPIV environments where multiple WWNs share a physical host bus adapter port. When consumption exceeds a threshold of the initiator's bandwidth capacity, the system implements IO limiting to prevent overwhelming the initiator with return payload. Using FDMI information, the system identifies WWNs associated with the same physical port and manages bandwidth allocation across initiators through equal or weighted distribution. This prevents switch credit buffer overflow by controlling data transmission rates between storage ports and initiators. The solution addresses traditional single-WWN configurations and NPIV environments where multiple WWNs operate on a single physical port.

The application relates to the technical field of wireless communication, and discloses a wireless communication signal transmission system and method based on adaptive modulation, which comprises a likelihood ratio extraction module, a queue monitoring module, a parameter adaptive control module and a constellation mapping module; the likelihood ratio extraction module acquires a log-likelihood ratio sequence; the queue monitoring module determines a buffer queue depth; the parameter adaptive control module adjusts a sliding integral register accumulation period according to the buffer queue depth, and uses the sliding integral register to implement time domain integral processing on the log-likelihood ratio sequence to generate a channel quality representation parameter, and then determines a target modulation order; the application cross-layer correlates the data backlog level with the baseband statistical time scale, reduces the dependence on explicit channel state information feedback, reduces control signaling overhead, smoothes transient impulse noise interference through a dynamic accumulation mechanism, prevents buffer overflow, and improves the transmission net throughput rate of digital information in a high concurrency environment.

Apparatus and methods for improving throughput and reliability in a wireless network. In one embodiment, the apparatus and methods provide mechanisms for wireless user device buffer management that mitigate buffer overflow within the device due to overscheduling, such as from different networks with which the device is connected simultaneously. In one variant, a 3GPP-based signaling architecture from wireless device to the multiple networks is provided to enable user device-controlled management buffer overflow. In another variant, potentially buffer-demanding (e.g., HARQ) process management and prioritization rules are defined to avoid buffer overflow. In other variant, buffer size computation is provided considering the number of networks to which the wireless user device can connect.

To prevent malfunctions in device 10, which uses the measured values ​​from sensor 11 after storing them in buffer 12. [Solution] The device's control unit 13 performs overall processing including sensor acquisition processing 21 and measurement value usage processing 22. If the sensor acquisition processing 21 determines that the buffer 12 has overflowed, it creates space in the buffer and sets a first cool-down state valid for a predetermined period in the state storage unit 14. If the sensor measurement value does not meet predetermined conditions, it sets a second cool-down state valid for a predetermined period in the state storage unit 14. In the measurement value usage processing 22, it checks the cool-down state (23), and if it is valid, it skips all or part of the measurement value usage processing (24) (25). As a result, the device 10 performs a cool-down when the buffer 12 overflows or when an unexpected measurement value is measured, thus avoiding malfunctions resulting from the use of unreliable measurement values.

Packets to be transmitted from the network device are buffered in a queue in a first packet memory. In response to detecting congestion in the queue in the first packet memory, a group of a plurality of packets is transferred from the first packet memory to a second packet memory, the second packet memory being configured to buffer a portion of a service bandwidth supported by the network device. Before transmitting packets in the one or more groups of the plurality of packets from the network device, the packets in the one or more groups of the plurality of packets are transferred from the second packet memory back to the first packet memory. The packets transferred from the second packet memory back to the first packet memory are retrieved from the first packet memory and forwarded to one or more network ports for transmitting packets from the network device.

The invention relates to the technical field of network security protection, and discloses a network security protection method and system based on mimicry defense, and the method comprises the steps: carrying out the clustering analysis of a plurality of executive bodies, dividing each executive body into a reference executive body and a non-reference executive body, carrying out the buffer overflow attack test of the executive bodies through an attack code, obtaining attack behavior characteristics, calculating behavior similarity between the reference attack behavior characteristics and the non-reference attack behavior characteristics, and judging whether a non-reference executor has a potential vulnerability utilization path or not; according to the attack success rate of the attack code variation, judging whether the potential vulnerability utilization path is valid or not; and constructing a mimicry defense strategy according to the path characteristics of the vulnerability utilization path. According to the method, the influence of the difference of the micro-system structures of different executors on the buffer overflow attack is analyzed, the potential attack path is identified, and a more targeted mimicry defense strategy is formulated, so that the defense effect of the executors on the network attack is improved, and the security of system operation is ensured.

The invention provides a flexible lamp strip virtual debugging method and system based on digital twinning, and belongs to the technical field of digital twinning. The method comprises the steps of dynamically adjusting the resource occupancy rate of a computing unit and generating rendering configuration by judging if the fluctuation amplitude of a predicted frame rate sequence exceeds a preset threshold value, balancing the large-scale array debugging computing power demand and the debugging resource occupancy of a single lamp strip, and avoiding the waste of computing resources; by monitoring the ratio of the viewport resolution rendering data volume to the preset frame buffer area capacity, the overflow risk of the buffer area is avoided; by determining a rendering task priority execution sequence, multi-task parallel conflicts are coordinated. Therefore, dynamic allocation of virtual resources, multi-task ordered scheduling and accurate parameter management are realized, the resource utilization rate is remarkably improved, rendering delay is reduced, the debugging period is shortened, and the consistency and delivery quality of flexible lamp strip products are guaranteed.

The invention provides a data interaction method for computing a fast link (CXL) device. The data interaction method comprises the following steps: receiving a monitoring request or a writing request from a host by the CXL equipment; recording a target address pointed by the monitoring request or the writing request in a monitoring buffer of the CXL equipment by the CXL equipment; under the condition that the CXL equipment determines that the host has sent all monitoring requests or write requests or the monitoring buffer overflows, the CXL equipment sends a target address recorded in the monitoring buffer and a write pointer value corresponding to the target address to the host so as to request the host to send data in a host cache corresponding to the target address, therefore, the CXL equipment can receive the sent data; and when the CXL device determines that all the target addresses recorded in the listening buffer are sent to the host, the CXL device generates an emptying completion interrupt signal to indicate that data are received and written into the target addresses of the device memory.

The application relates to the technical field of computer security, and particularly discloses a graph neural network detection method for a FreeRTOS buffer overflow vulnerability, which comprises the following steps: obtaining source code of a known vulnerability type; pre-processing and function-level code segmentation are performed on the source code to obtain multiple function codes; a static analysis tool Joern is used to construct a code property graph of the function codes; the JSON text corresponding to the code property graph comprises node information and edge information; an adjacency matrix of the code property graph is constructed according to the code property graph, and a feature matrix of the node information is constructed according to the JSON text; and a graph neural network model is trained according to the adjacency matrix and the feature matrix to detect the buffer overflow vulnerability.

A security defending method and an electronic apparatus are disclosed. The security defending method is applicable in a coprocessor, including: receiving a jump destination encryption request for the operation task; using mask configuration to perform first mask processing on the first jump destination address value to obtain a first intermediate jump destination address value; performing an authentication operation based on the first jump destination storage address, a key reference value corresponding to the operation task and the first intermediate jump destination address value, to obtain a first encryption result value; using the mask configuration to perform second mask processing on the first encryption result value to obtain a first intermediate encryption result value; performing an authentication operation on the first intermediate encryption result value and the first jump destination address value to obtain a first encryption jump destination address value. The security defending method can prevent buffer overflow attacks.

The embodiment of the invention provides a system for balancing network transmission bandwidth, and the system comprises a state detection module which is configured to monitor a network transmission index and clock synchronization information; generating a network quality score based on the network transmission index and the clock synchronization information; the index detection module is composed of a sending end and a receiving end, and the sending end is configured to send audio data; the receiving end is configured to generate feedback data based on the received audio data and transmit the feedback data back to the transmitting end, and the feedback data comprises a buffer area change trend, the number of packet loss times caused by buffer area overflow and clock offset; the performance adjusting module is configured to determine a performance adjusting strategy based on the network quality score and the feedback data; and adjusting the audio transmission parameters based on the performance adjustment strategy.