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208results about How to "Guaranteed preservation quality" patented technology

PMOS transistor with compressive dielectric capping layer

A salicide layer is deposited on the source/drain regions of a PMOS transistor. A dielectric capping layer having residual compressive stress is formed on the salicide layer by depositing a plurality of PECVD dielectric sublayers and plasma-treating each sublayer. Compressive stress from the dielectric capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in the PMOS channel. To form a compressive dielectric layer, a deposition reactant mixture containing A1 atoms and A2 atoms is provided in a vacuum chamber. Element A2 is more electronegative than element A1, and A1 atoms have a positive oxidation state and A2 atoms have a negative oxidation state when A1 atoms are bonded with A2 atoms. A deposition plasma is generated by applying HF and LF radio-frequency power to the deposition reactant mixture, and a sublayer of compressive dielectric material is deposited. A post-treatment plasma is generated by applying HF and LF radio-frequency power to a post-treatment gas that does not contain at least one of A1 atoms and A2 atoms. Compressive stress in the dielectric sublayer is increased by treating the sublayer in the post-treatment plasma. Processes of depositing a dielectric sublayer and post-treating the sublayer in plasma are repeated until a desired thickness is achieved. The resulting dielectric layer has residual compressive stress.
Owner:NOVELLUS SYSTEMS

Method and apparatus for controlling reverse link interference rise and power control instability in a wireless system

InactiveUS6968201B1Call quality will deterioratePreserve quality of serviceEnergy efficient ICTPower managementInterference (communication)Transmitted power
A system and a method for reverse link power control in a wireless communications network generates power adjust commands for mobiles being served by a network base station in a centralized manner by considering overall system performance when an increased interference condition is detected. In one implementation, a base station power control processor adopts a modified reverse inner loop power control (RILPC) and/or a reverse outer loop power control (ROLPC) algorithm when an increased interference condition is detected. According to the modified RILPC algorithm, a percentage of power-up adjust commands which would normally be generated when Eb/No measurements for served mobiles do not meet target Eb/No levels are converted to power down-adjust commands, thereby forcing some mobiles to reduce transmit power, at least temporarily, to constrain interference. When the increased interference condition persists, the percentage of power-up adjust commands which are converted to power-down commands may be changed. According to the modified ROLPC algorithm, the power control processor adjusts target Eb/No levels in a centralized manner based on an overall system state so that only a limited number of target Eb/No levels are allowed to increase when frame erasures occur. By preventing a percentage of target Eb/No level increases, at least temporarily, when frame erasures occur, a percentage of power up-adjust commands are avoided. Therefore, a similar effect to that achieved by the modified RILPC is achieved. In accordance with still a further implementation of the present invention, the modified RILPC algorithm may be used in combination with the modified ROLPC algorithm to provide greater resistance to increased interference conditions.
Owner:LGS INNOVATIONS +1
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