System and method for improving bus access error based on RISC-V architecture

Abstract

The invention discloses a system for improving a bus access error based on RISC-V architecture. The system comprises an abnormal priority control module, an interrupt control module and a skip controlmodule. The system distributes interrupt numbers for the bus access error, takes the bus access error as interrupt sources for processing, and the abnormal priority control module is used for carrying out priority ranking on all abnormal types, selecting an abnormal type with the highest current priority and outputting the selected abnormal type to the skip control module; the interrupt control module is used for carrying out unified management on the bus access error and other interrupt sources, selecting the interrupt source with the highest current priority and outputting the interrupt source to the skip control module; and the skip control module is used for analyzing and processing input abnormal types, interrupt sources and unshielded interrupts and outputting analyzed and processedsignals to the processor core. According to the invention, abnormity report is changed to interrupt report for the bus access error, so that software control can be facilitated.

Description

Technical field [0001] The present invention relates to the technical field of low power consumption kernel interrupt and exception handling, in particular to an improved system and method based on RISC-V architecture bus access error. Background technique [0002] Interrupt mechanism (Interrupt), that is, the processor core is suddenly interrupted by other requests in the process of sequential execution of the program instruction stream and suspends the execution of the current program, and then goes to deal with other things, wait for it to finish other things, and then Return to the point where the program was interrupted to continue executing the previous program instruction flow. Among them, the "other request" that interrupts the processor's execution of the program instruction flow is called Interrupt Request, and the source of the interrupt request is called Interrupt Source. Normally, the main interrupt source is From peripheral hardware devices. The transfer of the pr...

AI Technical Summary

Problems solved by technology

Because in most processor architectures, load / store access errors are regarded as imprecise asynchronous errors, and exceptions cannot be masked, so load / store access errors and reporting exceptions will cause the program to be uncontrollable

[0009] In general, since load / store access errors are usually regarded as an imprecise asynchronous error, in the RISC-V architecture, load / store access error reporting exceptions will cause the program to be uncontrollable

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