42 results about "Non-maskable interrupt" patented technology

Methods and computer-executable components for real-time scheduling of CPU resources are disclosed. A performance counter determines when to allocate CPU resources to a thread. When it is time to allocate the CPU resources, the performance counter issues a maskable or non-maskable interrupt to an advanced programmable interrupt controller (APIC). The APIC then issues a maskable non-maskable interrupt to the CPU. In response to receiving the non-maskable interrupt, the CPU allocates resources to the thread. In addition, the disclosed methods and computer-executable components also: (a) allow scheduling of CPU resources such that real-time threads are guaranteed respective portions of time slots, (b) enable real-time scheduling on a non-real-time operating system, and (c) provide scheduling of CPU resources on a uni-processor machine such that at least first and second real-time threads dependent on one another are synchronized.

Methods and computer-executable components for real-time scheduling of CPU resources are disclosed. A performance counter determines when to allocate CPU resources to a thread. When it is time to allocate the CPU resources, the performance counter issues a maskable or non-maskable interrupt to an advanced programmable interrupt controller (APIC). The APIC then issues a maskable non-maskable interrupt to the CPU. In response to receiving the non-maskable interrupt, the CPU allocates resources to the thread. In addition, the disclosed methods and computer-executable components also: (a) allow scheduling of CPU resources such that real-time threads are guaranteed respective portions of time slots, (b) enable real-time scheduling on a non-real-time operating system, and (c) provide scheduling of CPU resources on a uni-processor machine such that at least first and second real-time threads dependent on one another are synchronized.

Systems, apparatuses, and methods for intentionally delaying servicing of interrupts in a computing system are disclosed. A computing system includes a processor that services interrupts generated by components of the computing system. An interrupt controller detects a received interrupt and intentionally delays servicing of the interrupt depending on various conditions. If the interrupt is a first type of interrupt and the processor is in a first power state, servicing of the interrupt is delayed by a first period of time. If the interrupt corresponds to the first type of interrupt and the processor is in a second power state, servicing of the interrupt is delayed for a period of time that is longer than the first period of time. If a non-maskable interrupt is received before expiration of either the first or second period of time, then servicing of any previously delayed interrupts is allowed to proceed.

An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

The invention provides an input / output (I / O) framework expanding method based on a standard PCIe upstream port. Layering multistage bus expansion of the standard PCIe upstream port is used. A PCIe bus is arranged in a first stage, a PCI bus is arranged in a second stage, and a traditional bus is arranged in a third stage, wherein a basis input / output system (BIOS) is arranged in the traditional bus in a hanging mode. Initial configuration required by an SW processor and initial execution codes required by the SW processor are injected through a synchronous serial access out of a band, the initial execution codes achieve access configuration of a traditional device through only once depth-first enumeration, and the SW processor is enabled to rapidly obtain contents of the BIOS. Non-maskable interruption can be sent to a central processing unit (CPU) through the synchronous serial access out of the band, and be used for the aims of waking-up in a sleep state and the like.

In the present invention, when an abnormality occurs in a task, regardless of whether a critical section is being executed, timeout detection is realized by determining whether the critical section (CS) is necessary for the design in a preset task execution time and a certain period of time to distinguish between necessary interrupt disable and abnormal interrupt disable. A vehicle control device includes task execution means for causing a system to execute a task, and interrupt processing means for performing an interrupt process at the time of execution of the task. A maskable interrupt and a non-maskable interrupt that is commanded to execute after the maskable interrupt are included, the maskable interrupt is commanded to execute during an interrupt disable time, and then the non-maskable interrupt is executed.

A conversion transmission circuit of a non-maskable interrupt request is used to transmit the non-maskable interrupt request among a south bridge, a BMC, a first chip and a north bridge, which comprises a switch, an electrical level conversion module and a logic and electrical level conversion module, wherein the switch comprises a first end, a control end and a second end, the first end is grounded, the control end is coupled with the south bridge for receiving the control of the non-maskable interrupt request of the south bridge to conduct the first end and the second end. The electrical level conversion module comprises a first diode and a second diode, wherein the first diode is respectively coupled with the second end and a first power supply voltage through a first resistance after connecting with the positive electrode of the second diode, the negative electrode of the first diode is respectively coupled with the BMC and is coupled with the grounding voltage through a second resistance, and the negative electrode of the second diode is respectively coupled with the first chip and is coupled with the ground through a third resistance. The logic and electrical level conversion module is used to reversely transmit the signal of the input end to output, and makes the high electrical level to be in accordance with the electrical level of a second power supply voltage.

A processor of an aspect includes a decode unit to decode an exception handler return instruction. The processor also includes an exception handler return execution unit coupled with the decode unit. The exception handler return execution unit, responsive to the exception handler return instruction, is to not configure the processor to enable delivery of a subsequently received nonmaskable interrupt (NMI) to an NMI handler if an exception, which corresponds to the exception handler return instruction, was taken within the NMI handler. The exception handler return execution unit, responsive to the exception handler return instruction, is to configure the processor to enable the delivery of the subsequently received NMI to the NMI handler if the exception was not taken within the NMI handler. Other processors, methods, systems, and instructions are disclosed.

The embodiment of the present application discloses a method and device for processing the linux kernel. By obtaining the non-maskable interrupt NMI, in response to the interrupt, the debugging information of the linux kernel is obtained, and / or, in response to the interrupt, a preset operation is performed on the linux kernel . Since NMI is an interrupt that the processor cannot mask, when the code in the kernel mode fails and causes a system exception, the processor can still obtain the NMI interrupt. In response to the NMI, the processor can obtain the debugging information of the linux kernel and / or The kernel performs preset operations. Among them, by analyzing the debugging information of the linux kernel, the debugging method of the kernel state code can be obtained, so as to realize the debugging of the kernel state code, and the adjustment of the linux kernel can be realized by performing preset operations on the linux kernel, so as to alleviate code failures The impact on the linux kernel is conducive to the acquisition of debugging information and the debugging of kernel mode code, and improves the stability of linux kernel operation.

A computer-implemented method, data processing system, and processor for thermal regulation control with minimal impact on interrupt latency are provided. Monitors the setting of the interrupt status bit. In response to setting the interrupt status bit, it is determined whether the interrupt associated with the interrupt status bit is an unmasked interrupt. In response to an unmasked interrupt, the existing regulation mode is disabled and the interrupt is processed, wherein the interrupt latency of the integrated circuit is reduced. Monitors the clearing of the interrupt status bits. In response to clearing the interrupt status bit, the existing regulation mode is enabled.