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Patching method and patching device under multi-core environment

A patch and environment technology, applied in the field of patch methods and patch devices in a multi-core environment, can solve problems such as software logic confusion and errors, and achieve the effect of low synchronization time overhead and high reliability

Active Publication Date: 2009-10-21
HUAWEI TEHCHNOLOGIES CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

That is, in the multi-core AMP shared code segment environment, the patch operation needs to modify two instructions at the same time, and in the multi-core AMP shared code segment environment, if the software on a VCPU is patched, if the first patched original function has just been modified instruction, and the other VCPUs of this VCPU shared code segment just start to execute the patch function, at this time, the first instruction of the patch function executed by other VCPU is to patch the new function, and the second instruction is to patch the original function, which will cause The software logic is confused and errors occur
[0006] Therefore, in the multi-core AMP shared code segment environment, patching the software on one VCPU will affect other VCPUs that share the code segment with this VCPU. How to ensure that the patches of a group of VCPUs that share the code segment take effect at the same time is the multi-core AMP shared code Issues to be solved by patch technology in segmented environment

Method used

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  • Patching method and patching device under multi-core environment

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Experimental program
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Embodiment 1

[0026] An embodiment of the present invention provides a patch device in a multi-core environment. Wherein, the patch device of the embodiment of the present invention is applied to a multi-core AMP system, figure 1 It is a logical schematic diagram of a multi-core AMP system in this embodiment, such as figure 1 As shown, from the perspective of the logic layer, the bottom layer is a multi-core processor hardware platform, including multiple VCPUs, such as VCPU0, VCPU1, VCPU2 and VCPU3; the middle layer is the operating system layer, and an independent operating system RTOS runs on each VCPU; Above the operating system layer is the APP application layer.

[0027] The VCPU of this embodiment is divided into a management VCPU and a target VCPU according to different functions. In this embodiment, the management VCPU is VCPU0, and other VCPUs (VCPU1, VCPU2, and VCPU3) of the shared code segment are the target VCPUs, and there are multiple VCPUs with the shared code segment. The...

Embodiment 2

[0059] This embodiment provides a patch method in a multi-core environment, the architecture of the multi-core environment can be found in figure 1 , the patching method in this embodiment includes a patching method applied to a patching device of a management VCPU and a patching method applied to a patching device of a target VCPU. The method of this embodiment realizes the synchronous activation of the patch on the target VCPU through the inter-core synchronization mechanism, and realizes the effective patch of the target VCPU in exception handling.

[0060] Figure 5 It is a schematic flow chart of a patch method in a multi-core environment in an embodiment of the present invention. It should be noted that the patch method in this embodiment can be applied to a patch device for managing VCPUs, such as Figure 5 Shown:

[0061] Step S501, sending an inter-core non-maskable interrupt to each target virtual CPU in the shared code segment target virtual CPU group, so that the...

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Abstract

The embodiment of the invention provides a patching method and a patching device under multi-core environment; the patching method comprises the steps of sending internuclear non-maskable interrupt to each target-virtual CPU of a shared code segment target-virtual CPU group so as to cause the target-virtual CPUs to respond to the internuclear non-maskable interrupt and enter a patching synchronization state, monitoring the patching synchronization state of the target-virtual CPUs, changing the first command of the patched primitive function of the target-virtual CPUs into an abnormal command after all target-virtual CPUs enter the patching synchronization state, and outputting an notice on the finishing of the patching synchronization state to all target-virtual CPUs so as to shift the patched primitive function to a new patching function while the patched primitive function is executed to an abnormity handling process triggered by the abnormal command. The method and the device adopt the synchronous mode of internuclear non-maskable interrupt to realize the patching synchronous activation of the target-virtual CPUs of the shared code segment and realize the complete effectiveness of patches during the abnormal handling process.

Description

technical field [0001] The invention relates to the technical field of communications, in particular to a patch method and a patch device in a multi-core environment. Background technique [0002] Multi-core technology has become a new direction for the development of processor technology. At present, the road signs of mainstream processor manufacturers are multi-core processors. For example, the XLR732 processor of the MIPS (Microprocessor Without Interlocked Pipeline Stages: processor without interlocking pipeline stage) architecture launched by RAZA has 8 cores, each core contains 4 hardware threads (virtual CPU, VCPU), a total of 32 VCPU, the Cavium5860 processor of OCETON's MIPS architecture has 16 cores, and each core contains 1 VCPU. [0003] The operating system generally has two architectures on the multi-core processor hardware platform, one is SMP (Symmetrical Multi-Processing, Symmetrical Multi-Processing) mode, and the other is AMP (Asymmetrical Multi-Processin...

Claims

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Application Information

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IPC IPC(8): G06F9/445G06F9/48
CPCG06F8/67G06F8/65G06F8/656
Inventor 殷罗英叶鹏
Owner HUAWEI TEHCHNOLOGIES CO LTD
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