An IO extension architecture method based on standard pcie uplink port

A technology for extending the architecture and PCI devices, which is applied in the field of IO expansion architecture based on standard PCIe uplink ports, and can solve the problems that Shenwei processors cannot

Active Publication Date: 2015-08-12
JIANGNAN INST OF COMPUTING TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the Shenwei processor does not use the proprietary system bus of foreign companies, but it integrates the standard PCIe root complex to take advantage of numerous external devices on the market, and there is no interface for directly connecting traditional devices
Shenwei processors cannot access traditional devices as soon as they are powered on

Method used

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  • An IO extension architecture method based on standard pcie uplink port
  • An IO extension architecture method based on standard pcie uplink port
  • An IO extension architecture method based on standard pcie uplink port

Examples

Experimental program
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Embodiment approach

[0059] refer to Figure 5 As shown, one embodiment of the system startup method of the present invention includes: mini-BMC self-test 401, system configuration saving 402, initial configuration of Shenwei processor 403, initialization of Shenwei processor 404, BIOS path construction 405, fetching BIOS and executing 406.

[0060] Each step will be specifically described below.

[0061] mini-BMC self-test 401: After power-on (including standby power), it is the first to execute, including the self-test of the mini-BMC's own operating environment and the detection of system configuration. When the system is ready to start, perform the next step. System configuration save 402;

[0062] System configuration saving 402: mini-BMC saves some information needed for system start-up in Flash ROM, and then allows the maintenance module to perform the next step based on the information, and initially configures the Shenwei processor 403;

[0063] Initial configuration of Shenwei process...

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Abstract

The invention provides an input / output (I / O) framework expanding method based on a standard PCIe upstream port. Layering multistage bus expansion of the standard PCIe upstream port is used. A PCIe bus is arranged in a first stage, a PCI bus is arranged in a second stage, and a traditional bus is arranged in a third stage, wherein a basis input / output system (BIOS) is arranged in the traditional bus in a hanging mode. Initial configuration required by an SW processor and initial execution codes required by the SW processor are injected through a synchronous serial access out of a band, the initial execution codes achieve access configuration of a traditional device through only once depth-first enumeration, and the SW processor is enabled to rapidly obtain contents of the BIOS. Non-maskable interruption can be sent to a central processing unit (CPU) through the synchronous serial access out of the band, and be used for the aims of waking-up in a sleep state and the like.

Description

technical field [0001] The invention relates to the fields of computer and communication, in particular, the invention relates to an IO expansion architecture method based on a standard PCIe uplink port. Background technique [0002] At present, systems based on X86 processors use proprietary system buses, such as Intel's QPI bus and AMD's HT bus. Traditional devices are connected to the DMI or A-Link extended from the system bus, and the PCIe / PCI bridge circuit also Hanging on the system bus, the logical relationship is as follows figure 1 shown. [0003] X86 processor A1 can access traditional devices (including BIOS) A3 as soon as it is powered on, and configure PCIe / PCI channels and devices through PCIe / PCI bridge A2 during BIOS execution. [0004] However, the Shenwei processor does not use the proprietary system bus of foreign companies, but it integrates the standard PCIe root complex to take advantage of numerous external devices on the market, and there is no inte...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/20
Inventor 吴新军丁琳韩娇罗茂盛卢姝颖吴志勇欧阳伟
Owner JIANGNAN INST OF COMPUTING TECH
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