The invention discloses a weak physical non-clone function circuit utilizing NMOS process deviation, including a decoding circuit, sequencing circuit, an array of PUF cells and n shared head circuits,the PUF cell array is formed by arranging m plus n PUF cells in m rows and n columns, a PUF unit includes a first NMOS transistor, second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor and the aspect ratios of the four PMOS transistors are all minimum sizes in the TSMC 65 nm process: 120nm/60nm, each shared head circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first two-input NAND gate and a second two-input NAND gate. The aspect ratios of the four NMOS transistors range from 2um/60nm to 16um/60nm. The utility model has the advantages of small area, low power consumption, small delay and high speed on the basis of the reset function.