A weakly physically non-clonable function circuit utilizing NMOS process deviations

Abstract

The invention discloses a weak physical non-clone function circuit utilizing NMOS process deviation, including a decoding circuit, sequencing circuit, an array of PUF cells and n shared head circuits,the PUF cell array is formed by arranging m plus n PUF cells in m rows and n columns, a PUF unit includes a first NMOS transistor, second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor and the aspect ratios of the four PMOS transistors are all minimum sizes in the TSMC 65 nm process: 120nm/60nm, each shared head circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first two-input NAND gate and a second two-input NAND gate. The aspect ratios of the four NMOS transistors range from 2um/60nm to 16um/60nm. The utility model has the advantages of small area, low power consumption, small delay and high speed on the basis of the reset function.

Description

technical field [0001] The invention relates to a physically unclonable function circuit, in particular to a weakly physically unclonable function circuit utilizing NMOS process deviation. Background technique [0002] Physically unclonable functions (PUFs) can guarantee information security at the physical level of chips, so they have received more and more attention. The physical unclonable function circuit is a very promising embedded key generation circuit, which can generate a series of output keys with randomness, uniqueness and unclonability by capturing the random process deviation of PUF units. These output keys can be applied in the field of information security, such as key generation, device authentication and IP protection, etc. [0003] Currently, physical unclonable function circuits are generally divided into two categories: weak PUF circuits and strong PUF circuits. In a weak PUF circuit, each PUF unit usually generates a one-bit output response, and the o...

AI Technical Summary

Problems solved by technology

However, the weak PUF circuit implemented by the SRAM-PUF unit disclosed in Document 1 has the following problems: 1. The key generated after the SRAM-PUF is powered on cannot be reset; 2. The SRAM-PUF unit contains 6 MOS transistors (2 PMOS tube and 4 NMOS tubes), the number of MOS tubes used is large, and in order to ensure that the SRAM-PUF unit can be read and written normally, the 6 MOS tubes need to use ratio logic, so that the MOS tubes cannot use the minimum process size, and the 6 There are both PMOS transistors and NMOS transistors in the MOS transistors, which ultimately leads to a large area of ​​the weak PUF circuit implemented by the SRAM-PUF unit and high power consumption.

Although the weak PUF circuit realized by the SRAM-PUF unit with reset function disclosed in Document 2 has a reset function, it also has the following problems: 1. The SRAM-PUF unit with reset function includes 10 MOS transistors ( 4 PMOS tubes and 6 NMOS tubes), the number of MOS tubes used is large, and there are both PMOS tubes and NMOS tubes in the 10 MOS tubes, which eventually leads to the weak PUF realized by the SRAM-PUF unit with reset function The circuit area is large and the power consumption is high; Second, due to the stacking effect of the PMOS tube, the node 'Q / QB' takes a long time to transition from the transient state to the bistable state, which has a negative impact on the speed

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