Face recognition acceleration circuit system and acceleration method based on RISC-V

A RISC-V, face recognition technology, applied in character and pattern recognition, instruments, biological neural network models, etc., can solve the problem of unfavorable algorithm end-based rapid deployment, expensive ISA authorization, project cost control and development cycle budget It is difficult to meet expectations and other problems to achieve the effect of improving the efficiency of imitation storage and speeding up the calculation process

Active Publication Date: 2019-11-12
SHANDONG INSPUR SCI RES INST CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, on the road to siliconization of convolutional neural networks, the microprocessor IP core used for algorithm flow control generally uses the ARM instruction set, and its ISA authorization is expensive and requires a certain development cycle, which is not conducive to the rapid deployment of algorithm terminals. , it is difficult to meet expectations in terms of project cost control and development cycle budget

Method used

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  • Face recognition acceleration circuit system and acceleration method based on RISC-V
  • Face recognition acceleration circuit system and acceleration method based on RISC-V

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Experimental program
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Effect test

Embodiment 1

[0033] A face recognition acceleration circuit system based on RISC-V, including an image acquisition module, a RISC-V kernel module, an instruction processing module, an acceleration module, a parameter storage module, a storage control module and a face image processing module, and between each module communication connection;

[0034] The image acquisition module includes an image transcoding module and a data cache module;

[0035] The instruction processing module includes an instruction decoding module and a hardware acceleration instruction queuing module;

[0036] The face image processing module includes a database retrieval module and a display coding module;

[0037] The RISC-V kernel module is a microprocessor composed of an open source simplified instruction set architecture. The storage control module is hung on the control bus. According to the high-level language description of the face recognition algorithm, it is decoded by the compiler in the RISC-V kernel ...

Embodiment 2

[0046] On the basis of Embodiment 1, the parameters of the deep neural network include convolution kernel values, convolution kernel bias values, and convolution kernel activation thresholds for each layer of convolution;

[0047] The RISC-V kernel module controls the storage control module, and transmits the transcoded image information to the MACC dedicated acceleration module;

[0048] The RISC-V kernel module controls the MACC dedicated acceleration module to load the convolution kernel value, convolution kernel offset value, and convolution kernel activation threshold of each layer of convolution, and the MACC dedicated acceleration module controls the convolution kernel value and data cache module The image data is multiplied by the multiplication array, and after the product and the convolution kernel offset value are added and summed, the activation threshold of the convolution kernel is selected and output to obtain the face feature value; the convolution calculation i...

Embodiment 3

[0050] A face recognition acceleration method based on RISC-V, using the RISC-V core to build an open instruction set architecture to achieve face recognition acceleration;

[0051] The RISC-V core controls the process of transcoding and caching the data of each frame of the collected image information arranged in the form of each pixel RGB (8:8:8);

[0052] And control the process of translating and mapping the face recognition algorithm into multiplication acceleration instructions and access acceleration instructions, and temporarily storing the instructions in the order of reading;

[0053] At the same time, control the MACC dedicated acceleration module to use the multiplication acceleration instruction and the access acceleration instruction to accelerate the process of performing deep neural network parameter calculation on the transcoded image information to obtain the face feature value;

[0054] And control the search and comparison of the face feature value and the ...

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Abstract

The invention discloses a face recognition acceleration circuit system and acceleration method based on RISC-V, and belongs to the field of artificial intelligence data processing. The acceleration circuit system comprises an image acquisition module, an RISC-V kernel module, an instruction processing module, an acceleration module, a parameter storage module, a storage control module and a face image processing module, and all the modules are in communication connection. According to the acceleration identification circuit system, hardware operated by deep neural network parameters is lowered, the calculation process of the face recognition process is greatly accelerated, the imitation memory efficiency is improved. The RISC-V kernel reduced instruction set serves as an instruction set framework of the on-chip microcontroller and serves as face recognition hardware acceleration master control, the framework is autonomous and controllable, and the safety and privacy confidentiality ofthe face recognition acceleration circuit can be improved.

Description

technical field [0001] The invention discloses a face recognition acceleration circuit system and acceleration method based on RISC-V, and relates to the technical field of artificial intelligence data processing. Background technique [0002] RISC-V is an open instruction set architecture (ISA) based on the principle of reduced instruction set computing (RISC), from the University of California, Berkeley. As an outstanding representative of open source chip technology in recent years, the RISC-V open instruction set architecture has attracted extensive attention from various fields at home and abroad. Contrary to most ISAs, the RISC-V ISA is free to use in all desired devices, allowing anyone to design, manufacture and sell RISC-V chips and software. Based on the RISC-V instruction set architecture, it is possible to design server CPUs, household appliance CPUs, industrial control CPUs and CPUs used in small sensors. Compared with most instruction sets, the RISC-V instruc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06K9/00G06N3/04G06N3/063
CPCG06N3/063G06V40/172G06V40/168G06N3/045
Inventor 王子彤姜凯秦刚
Owner SHANDONG INSPUR SCI RES INST CO LTD
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