A non-shielding interrupt processing system and method suitable for a RISC-V architecture

A RISC-V, processing system technology, applied in the direction of program startup/switching, multi-program device, energy-saving computing, etc., can solve problems such as unrecoverable and unrecoverable

Active Publication Date: 2019-06-28
AMOLOGIC (SHANGHAI) CO LTD
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Problems solved by technology

In practical applications, if a non-masked interrupt occurs in an interrupt or exception service program, for the RISC-V architecture, the mepc registers automatically saved by the hardware when an interrupt occurs will be overwritten when a non-masked interrupt occurs, resulting in unrecoverable (non-recoverable)
Therefore, in the RISC-V architecture, if there is an interrupt or an unmaskable interrupt occurs in an exception, there will be an unrecoverable problem

Method used

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  • A non-shielding interrupt processing system and method suitable for a RISC-V architecture
  • A non-shielding interrupt processing system and method suitable for a RISC-V architecture
  • A non-shielding interrupt processing system and method suitable for a RISC-V architecture

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Embodiment Construction

[0045]The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0046] It should be noted that, in the case of no conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.

[0047] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

[0048] In the RISC-V architecture, the CSR register mtvec register, mcause register and mepc register are defined...

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Abstract

The invention relates to the technical field of low-power-consumption kernel interrupt processing, in particular to a non-shielding interruption processing system and method suitable for a RISC-V architecture, and the system comprises a mode register, an abnormal vector base address register, a state register, an abnormal return address register, an abnormal reason register, a non-shielding interruption vector base address register, a non-shielding interruption state register, and a non-shielding interruption return address register. Beneficial effects are as follows: the device is simple in structure; an abnormal vector base address register is interrupted through non-shielding; the state of the processor when the non-shielding interruption occurs is stored in the non-shielding interruption state register, the values of the abnormal vector base address register and the state register are not changed, nesting of the non-shielding interruption can be recovered, and it is further guaranteed that the system can recover after the non-shielding interruption occurs.

Description

technical field [0001] The present invention relates to the technical field of low power consumption kernel interrupt processing, in particular to a non-shielding interrupt processing system and method suitable for RISC-V architecture. Background technique [0002] Non-maskable interrupt (NMI, Non-Maskable Interrupt) is a special input signal of the processor core, which is often used to indicate an emergency error at the system level (for example, external hardware failure, etc.). After encountering a non-maskable interrupt, the processor core will immediately suspend the execution of the current program, and instead process the non-maskable interrupt error. [0003] In the prior art, after a non-masked interrupt occurs in the system, the core of the processor will have the following actions: (1) jump to the non-masked interrupt vector address defined by the system to handle the non-masked interrupt error; (2) the mepc register update become the address of the next instruc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/48
CPCY02D10/00
Inventor 吴俊顾冲李青
Owner AMOLOGIC (SHANGHAI) CO LTD
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