Integrated circuit collaborative layout method, device and equipment

Abstract

The invention provides an integrated circuit collaborative layout method, device and equipment, which are applied to the technical field of integrated circuit design, and are characterized in that a proper net model is selected through a net relationship, and a matrix and a vector of quadratic programming layout are constructed according to the net model, so that an initial unit layout is efficiently solved; a batch processing strategy is adopted to carry out overlapping optimization on a standard cell and a macro cell to generate a legalized layout solution, an interaction force between anchor point simulation units is introduced, the layout is continuously iterated and refined until the line length converges, and a final high-quality layout solution is obtained, so that the overall performance of a chip is improved, the power consumption is reduced, and the overall performance of the chip is improved. And the macro cells and the standard cells are distributed to different chips in the three-dimensional stacked structure, so that the requirement that different chip layers adopt different design processes is met, and the production cost is effectively reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and particularly to a method and device, and equipment for collaborative layout of integrated circuits. Background Art

[0002] In the Memory-on-Logic (MoL) scenario, macro cells and standard cells are hierarchically laid out in a three-dimensional space, allowing and even encouraging overlap between macro cells and standard cells. This overlapping relationship helps to shorten the data transmission path, thereby improving chip performance and reducing data power consumption. In addition, this stacked structure also supports the use of different design processes for the upper and lower chips, which helps to further reduce production costs.

[0003] However, current academic research on the layout in the MoL scenario is not sufficient. Most existing research on three-dimensional integrated circuit (3D-IC) scenarios mainly focuses on methods of simultaneously distributing macro cells and standard cells on two stacked chips, such as reference [1]; research on the MoL scenario mostly stays at the overall process framework and lacks in-depth discussion on the application of specific algorithms, such as references [2-3]; moreover, due to differences in optimization objectives, the existing 3D Mixed-Size Placement algorithm cannot be directly applied to the MoL scenario.

[0004] In addition, traditional secondary layout algorithms mainly rely on the attraction of net connections and the repulsion generated by cell overlap to generate layout solutions through iterative optimization. During the optimization process, the overlapping relationship between cells is considered, and the repulsion mechanism is used to prevent cell overlap. However, in the MoL scenario, overlap between macro cells and standard cells is allowed and even beneficial. Therefore, traditional algorithms will unnecessarily introduce repulsion in this scenario, attempting to avoid overlap between macro cells and standard cells, resulting in too far a distance between macro cells and standard cells, increasing the length of the data transmission path, reducing performance, and increasing power consumption, which conflicts with the design objectives of the MoL scenario.

[0005] Based on this, a new method for collaborative layout of integrated circuits is needed.

[0006] References:

[0007] [1] Huang Tongtong, Chen Hao, Wu Chenfei, et al. Application of concurrent multi-die optimization method in physically implematation[J]. Application of Electronic Technique, 2023, 49(8): 30-35.

[0008] [2] Huang Tongtong, Chen Hao, Wu Chenfei, et al. Application of concurrent multi-die optimization method in physically implematation[J]. Application of Electronic Technique, 2023, 49(8): 30-35.

[0009] [3] BAMBERG L, ORTIZ A, ZHU L, et al. Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs[C]. 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020: 37-42. Summary of the Invention

[0010] In view of this, embodiments of this specification provide a method, device, and equipment for collaborative layout of integrated circuits. By preserving the netlist connection relationship between macro cells and standard cells while separately considering the overlap relationships between standard cells and between macro cells, the quality of the overall layout solution is improved.

[0011] Embodiments of this specification provide the following technical solutions:

[0012] Embodiments of this specification provide a method for collaborative layout of integrated circuits, including:

[0013] Step S1: Select a netlist model based on the netlist connection relationship, and construct a matrix and a force vector for quadratic programming layout based on the netlist model;

[0014] Step S2: Solve for the position of each cell according to the matrix and the force vector to obtain an initial layout solution for the cells;

[0015] Step S3: Adopt a batch processing strategy to perform overlapping optimization operations on the standard cells and macro cells respectively, and generate a legalized layout solution;

[0016] Step S4: Use the legalized layout solution as an anchor point and add it to the netlist model to simulate the repulsive force between cells;

[0017] Iterate steps S1 to S4 until the wire length converges to obtain the final layout solution;

[0018] Step S5: According to the final layout solution, allocate the macro modules and standard cells to different chips in the three-dimensional stacked structure.

[0019] The embodiment of this specification also provides an integrated circuit co-layout device, including:

[0020] A construction module, configured to select a netlist model based on the net connection relationship, and construct a matrix and a force vector for quadratic programming layout based on the netlist model;

[0021] An initial layout solution generation module, configured to solve the position of each cell according to the matrix and the force vector to obtain an initial cell layout solution;

[0022] A batch processing module, configured to perform overlapping optimization operations on the standard cells and macro cells respectively to generate a legalized layout solution;

[0023] A repulsive force simulation module, configured to use the legalized layout solution as an anchor point and add it to the netlist model to simulate the repulsive force between cells;

[0024] An iteration control module, configured to repeatedly call the construction module, the initial layout solution generation module, the batch processing module, and the repulsive force simulation module until the wire length converges to obtain the final layout solution;

[0025] An allocation module, configured to allocate the macro modules and standard cells to different chips in the three-dimensional stacked structure according to the final layout solution.

[0026] The embodiment of this specification also provides an electronic device, including:

[0027] At least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute: the integrated circuit co-layout method described in any one of this application.

[0028] Compared with the prior art, the at least one technical solution adopted in the embodiment of this specification can achieve at least the following beneficial effects:

[0029] Select a suitable wire network model based on the wire network relationship, and construct the matrix and vector for quadratic programming layout accordingly, so as to efficiently solve the initial cell layout. Subsequently, adopt a batch processing strategy to perform overlapping optimization on standard cells and macro cells respectively to generate a legalized layout solution. Introduce anchor points to simulate the interaction forces between cells, and continuously iterate and refine the layout until the wire length converges to obtain the final high-quality layout solution, which not only improves the overall performance of the chip and reduces power consumption, but also supports allocating macro cells and standard cells to different chips in a three-dimensional stacked structure to meet the requirements of using different design processes for different chip layers, effectively reducing production costs. Brief Description of the Drawings

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0031] Figure 1 It is a schematic diagram of the integrated circuit co-layout method in the present application;

[0032] Figure 2 It is the process of converting the original two-dimensional layout into a three-dimensional layout through co-layout in the MoL scenario of the present application;

[0033] Figure 3 It is the overall flowchart of the integrated circuit co-layout method in the present application;

[0034] Figure 4 It is a schematic diagram of the repulsive force direction when macro cells and standard cells overlap in the MOL scenario of the present application. Detailed Embodiments

[0035] The embodiments of the present application will be described in detail below with reference to the drawings.

[0036] The following illustrates the implementation manners of the present application through specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of them. The present application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts belong to the scope of protection of the present application.

[0037] It should be noted that the following describes various aspects of embodiments within the scope of the appended claims. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is illustrative only. Based on this application, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement a device and / or practice a method. Additionally, this device and / or method can be implemented using other structures and / or functionality in addition to one or more of the aspects set forth herein.

[0038] It should also be noted that the diagrams provided in the following embodiments only schematically illustrate the basic concept of this application. The diagrams only show the components related to this application and are not drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0039] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the examples can be practiced without these specific details.

[0040] In the memory-on-logic (MoL) scenario of three-dimensional integrated circuits (3D-ICs), it is necessary to place macro cells and standard cells collaboratively. It is required that the macro cells (such as memories) overlap as much as possible with the connected standard cells (such as logic circuits). For example, the macro cells are placed above the standard cells, i.e., in the top die, so as to minimize the horizontal distance between the two under three-dimensional stacking, shorten the interconnect path, and reduce power consumption. However, existing 3D-IC layout research mostly targets the two-chip scenario where macro cells and standard cells are evenly distributed, that is, each chip layer contains macro cells and standard cells to achieve the overall performance and power consumption balance, and cannot be directly applied to the MoL scenario.

[0041] In view of this, the inventors have found through research and improvement exploration that: traditional secondary layout algorithms will consider the overlapping relationship between cells during the optimization process and forcefully avoid all cell overlaps through repulsive forces, resulting in too large a distance between macro cells and standard cells, thereby increasing the length of the data transmission path, reducing performance, and increasing power consumption.

[0042] Based on this, the embodiments of this specification propose an integrated circuit collaborative layout method. The overall idea is: as Figure 1As shown, by selecting an appropriate wire network model to construct a quadratic programming matrix and a force vector, an initial layout solution is generated. Subsequently, a batch processing strategy is adopted to optimize the overlap problems of standard cells and macro cells respectively, generating a legalized layout solution and dynamically introducing it into the model as an anchor point. The repulsive force is simulated to balance the cell spacing, and the repulsive force of the overlapping cells is optimized through iteration to generate a reasonable layout solution that meets the requirements of the MoL scenario. Finally, the macro cells and standard cells are hierarchically allocated to different chips in a three-dimensional stacked structure, thereby allowing controllable overlap of heterogeneous cells to shorten the interconnection path while avoiding layout congestion of homogeneous cells, improving the overall performance of the chip, and reducing power consumption and production costs.

[0043] The layout planning process in the MoL scenario is as Figure 2 shown. First, the macro cells and standard cells are placed synchronously on a two-dimensional plane using a co-layout algorithm, and then the results of the two are split onto two chips.

[0044] The following combines the accompanying drawings to illustrate the technical solutions provided by the embodiments of the present application.

[0045] As Figure 1 shown, an embodiment of this specification provides an integrated circuit co-layout method, including:

[0046] Step S1: Select a wire network model based on the wire network connection relationship, and construct a matrix and a force vector for quadratic programming layout based on the wire network model.

[0047] Specifically, in the design of an integrated circuit (IC), the wire network connection relationship describes the electrical connections between various units (such as standard cells and macro cells) in the circuit, directly affecting the signal transmission path and the performance of the circuit.

[0048] Select an appropriate wire network model for modeling according to the wire network connection relationship. For example, the Star model, the Clique model, or the Bound-to-Bound (B2B) model. Once the wire network model is selected, the next step is to construct the matrix and the force vector of the quadratic programming problem according to this model.

[0049] Step S2: Solve the position of each unit according to the matrix and the force vector to obtain an initial layout solution of the unit.

[0050] Specifically, as Figure 3 shown, the wire network connection attracts the interconnected units to approach, and at the same time, the movement range is restricted by the results of the previous round of movement. The position of each unit is solved, and the current solution is used as the initial layout solution for the next round of iteration.

[0051] Step S3: Adopt a batch processing strategy to perform overlap optimization operations on standard cells and macro cells respectively to generate a legalized layout solution.

[0052] Specifically, a layout algorithm considering overlap is synchronously used to optimize the positions of standard cells and macro cells with overlap, respectively generating a layout solution with the minimum total overlap area, that is, a legalized layout solution, and gradually reducing the overlap rate.

[0053] Step S4: Use the legalized layout solution as an anchor point and add it to the wire network model to simulate the repulsive force between cells, thereby constraining the action of the attractive force, so as to ensure that each cell has enough space to be placed and avoid physical conflicts;

[0054] Iterate steps S1 to S4 until the wire length converges to obtain the final layout solution.

[0055] Specifically, the legalized layout solution after each overlap problem is solved will be used for the next iteration to generate an appropriate repulsive force to further optimize the cell positions. In this way, a layout solution that meets the subsequent legalization requirements can be generated to the greatest extent, not only improving the quality of the solution, but also effectively reducing the pressure and complexity of subsequent optimization.

[0056] The wire length convergence judgment criterion can be: when the change rate of the wire length is lower than a preset threshold; or when a preset number of iterations is reached.

[0057] Step S5: According to the final layout solution, allocate the macro modules and standard cells to different chips in the three-dimensional stacked structure.

[0058] Specifically, the final layout solution is determined through iterative optimization, thereby determining the final positions of the macro cells and standard cells, and then further allocating the macro modules and standard cells to different chips in the three-dimensional stacked (3D-IC) structure, and outputting the specific layout coordinates of the macro cells and standard cells in each chip, which not only optimizes the data transmission path, improves the chip performance, but also reduces the power consumption and helps to reduce the production cost.

[0059] In some embodiments, taking the horizontal direction as an example, the objective function of the quadratic programming layout is:

[0060]

[0061] where M represents the quadratic term matrix in the quadratic objective function, b is the force vector corresponding to the linear term, x represents the abscissa vector of the cell position in the two-dimensional plane, y represents the ordinate vector of the cell position in the two-dimensional plane, x T is the transpose of the vector x, and M and b are constructed according to the wire network connection relationship and the anchor points generated in the previous iteration.

[0062] In implementation, the matrix M is constructed based on the weights of the interconnected wire networks. In the MoL scenario, since the goal of minimizing the wire length in quadratic programming is still reasonable, the actual objective function can be equivalent to the objective function in the two-dimensional plane scenario.

[0063] In some embodiments, the wire network model includes: a boundary-to-boundary model.

[0064] In implementation, to simplify the modeling and reduce the computational complexity, for the construction of the matrix and the force vector, a boundary-to-boundary model (bound-to-bound, B2B) model can be used for modeling to fully represent the interconnection relationship between pins.

[0065] In some embodiments, the matrix and the force vector are the matrix and the force vector required by the conjugate gradient method;

[0066] Solving for the position of each cell includes: using the conjugate gradient method to solve for the position of each cell, and the position of each cell will be used as the initial input for the next iteration.

[0067] In some embodiments, when performing overlap optimization operations on standard cells and macro cells respectively, by adjusting the direction of the repulsive force between cells, overlap constraints are applied only between cells of the same type, and no repulsive force is generated between the macro cell and the standard cell.

[0068] In implementation, layout optimization algorithms considering overlap relationships are separately applied to standard cells and macro cells respectively, so as to reduce the number of overlapping cells and the overlapping area. This operation is equivalent to separately performing a rough legalization operation on standard cells and macro cells on two chips.

[0069] In Figure 4 , it can be observed that due to the characteristics of the MoL scenario, the standard cells in the lower right of the figure are not subject to repulsive force because the macro cell and the standard cell do not actually belong to the same chip, so they do not occupy space with each other.

[0070] In some embodiments, the anchor point weights are updated according to the cell size, position, and number of iterations;

[0071] According to the anchor point weights, update the matrix and the force vector corresponding to the quadratic programming layout:

[0072] m ii += Weight anchor ;

[0073] b[i] += x anchor * Weight anchor ;

[0074] where, m ii represents the diagonal element of matrix M, Weight anchor represents the anchor point weight, b[i] represents the linear term coefficient related to the i-th cell, and x anchor represents the position of the anchor point.

[0075] Combined with the above embodiments, the position of each unit after legalized movement will serve as an anchor point and be assigned a corresponding anchor point weight. This weight will be adjusted according to changes in module size, position, and the number of iterations. Generally, as the number of iterations increases, the weight of the anchor point will gradually increase. Finally, this weight will be added to the corresponding elements of the matrix and the force vector in the next iteration to simulate the overlapping repulsive force received by the unit and limit the mutual attractive movement of the units.

[0076] In some embodiments, in step S5, the vertical connection relationship of the three-dimensional stacked structure is modeled by the following formula:

[0077] W e (v) = l e (x) + l e (y) + α * l e (z);

[0078] where e represents the wire net; v represents the coordinates of the unit; l e (x) + l e (y) represents the half perimeter length of the two-dimensional plane; α represents the vertical connection weight; l e (z) represents the vertical connection distance in the three-dimensional scenario.

[0079] In implementation, in the 3D-IC scenario, in addition to the default horizontal connection relationship, a vertical connection relationship representing inter-chip connection processes such as Hybrid bonding is additionally added. The maximum or minimum value of the vertical connection distance is usually set according to circuit performance requirements, manufacturing process limitations, and design constraints.

[0080] In the layout planning stage, since more attention needs to be paid to the potential impact brought by the movement of macro cells, and the additional delay introduced by the vertical connection is relatively small compared to the internal connection delay of the chip, in some embodiments, a basic HPWL model can be used for modeling, which can make the parameter α = 0, and the 3D HPWL model will degenerate into a 2D HPWL model.

[0081] In some embodiments, the allocating the macro module and standard cells to different chips of the three-dimensional stacked structure includes:

[0082] Allocating the macro cell to the top chip of the three-dimensional stacked structure;

[0083] Allocating the standard cell to the bottom chip.

[0084] Specifically, after the iteration ends, by dividing the macro cell into the top die, the two chips are truly split, completing the entire design process, ensuring the connection effectiveness between different chips, and providing a good foundation for subsequent layout optimization.

[0085] Based on the same inventive concept, the present application also provides an integrated circuit co-layout device corresponding to the foregoing method example, including:

[0086] A construction module, configured to select a net model based on a net connection relationship, and construct a matrix and a force vector for quadratic programming layout based on the net model;

[0087] An initial layout solution generation module, configured to solve the position of each cell according to the matrix and the force vector to obtain an initial cell layout solution;

[0088] A batch processing module, configured to perform overlapping optimization operations on standard cells and macro cells respectively to generate a legalized layout solution;

[0089] A repulsive force simulation module, configured to use the legalized layout solution as an anchor point and add it to the net model to simulate the repulsive force between cells;

[0090] An iteration control module, configured to repeatedly call the construction module, the initial layout solution generation module, the batch processing module, and the repulsive force simulation module until the wire length converges to obtain a final layout solution;

[0091] An allocation module, configured to allocate macro modules and standard cells to different chips of a three-dimensional stacked structure according to the final layout solution.

[0092] Based on the same inventive concept, the present application also provides an electronic device based on the integrated circuit co-layout method. The device includes: a processor, a memory, and a computer program; wherein

[0093] The memory is used to store the computer program, and the memory can also be a flash memory. The computer program is, for example, an application program or a functional module that implements the foregoing method.

[0094] The processor is configured to execute the computer program stored in the memory to implement each step performed by the device in the foregoing method. For specific details, reference can be made to the relevant descriptions in the foregoing method embodiments.

[0095] Optionally, the memory can be either independent or integrated with the processor.

[0096] When the memory is a device independent of the processor, the device may further include:

[0097] A bus, configured to connect the memory and the processor.

[0098] Based on the wire network connection relationship, this application elaborates on the motivation for selecting a specific wire network model and conducts modeling, so as to use the attraction mechanism to make the associated units approach each other, thereby effectively minimizing the total half-perimeter (HPWL) and improving the performance of the layout.

[0099] This application adopts a batch processing strategy to separately solve the overlap problem between standard cells and macro cells, and gradually reduce the overlap rate. The layout solution after each overlap problem is solved will be used for the next iteration to generate a moderate repulsive force to further optimize the cell positions. In this way, a layout solution that meets the subsequent legalization requirements is generated to the greatest extent, not only improving the quality of the solution, but also effectively reducing the pressure and complexity of subsequent optimization.

[0100] Given macro cells and standard cells, based on the quadratic programming method, this application controls the magnitude of the repulsive force received by the overlapping cells after each movement by modifying the overlap influence between macro cells and between standard cells, and gradually optimizes the layout. Finally, the macro cells and standard cells are truly split into two chips. This strategy not only fully considers the connection relationship between cells to ensure the coherence and rationality of the layout, but also meets the layout requirements in the MoL scenario, thereby generating a reasonable and high-quality initial layout solution to effectively guide the subsequent 3D-IC layout and routing optimization.

[0101] The collaborative optimization processing mode of this application is not only applicable to the MoL scenario, but can also be extended to the case where there are multiple chips and the chip to which each unit belongs is clear, thus greatly expanding the application prospect of this method.

[0102] In this specification, the same or similar parts between various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments described later, the description is relatively simple, and the relevant parts can be referred to the partial description of the foregoing embodiments.

[0103] The above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by this application should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

1. An integrated circuit co-layout method, characterized in that, including: Step S1: Select a wire network model based on the wire network connection relationship, and construct a matrix and a force vector for quadratic programming layout based on the wire network model; Step S2: Solve for the position of each cell according to the matrix and the force vector to obtain an initial cell layout solution; Step S3: Adopt a batch processing strategy to perform overlapping optimization operations on standard cells and macro cells respectively to generate a legalized layout solution; Step S4: Use the legalized layout solution as an anchor point and add it to the wire network model to simulate the repulsive force between cells; Iterate Steps S1 to S4 until the wire length converges to obtain a final layout solution; Step S5: According to the final layout solution, allocate macro modules and standard cells to different chips of a three-dimensional stacked structure.

2. The integrated circuit co-layout method according to claim 1, wherein The objective function of the quadratic programming layout is: where M represents the quadratic term matrix in the quadratic objective function, b is the force vector corresponding to the linear term, x represents the horizontal position vector of the unit in the two-dimensional plane, y represents the vertical position vector of the unit in the two-dimensional plane, and x T is the transpose of the vector x, and M and b are constructed according to the wire network connection relationship and the anchor points generated in the previous iteration.

3. The integrated circuit co-layout method according to claim 1, wherein The wire network model includes: a boundary-to-boundary model.

4. The integrated circuit co-layout method according to claim 1, wherein The matrix and the force vector are the matrix and force vector required by the conjugate gradient method; Solving for the position of each cell includes: using the conjugate gradient method to solve for the position of each cell.

5. The integrated circuit co-layout method according to claim 1, wherein, When performing overlapping optimization operations on standard cells and macro cells respectively, by adjusting the direction of the repulsive force between cells, only apply overlapping constraints between cells of the same type, and no repulsive force is generated for the overlap between macro cells and standard cells.

6. The integrated circuit co-layout method according to claim 1, wherein Update the anchor point weight according to the cell size, position and number of iterations; Update the matrix and force vector corresponding to the quadratic programming layout according to the anchor point weight: m ii += Weight anchor ; b[i]+=x anchor *Weight anchor ; where m ii represents the diagonal elements of matrix M, Weight anchor represents the anchor weight, b[i] represents the linear term coefficient associated with the i-th unit, and x anchor represents the position of the anchor point.

7. The integrated circuit co-layout method according to claim 1, wherein In Step S5, the vertical connection relationship of the three-dimensional stacked structure is modeled by the following formula: W e v) = l e x) + l e y) + α * l e z); Among them, e represents a wire network; v represents the coordinates of a cell; l e (x) + l e (y) represents the half perimeter length of a two-dimensional plane; α represents the vertical connection weight; l e (z) represents the vertical connection distance in a three-dimensional scene.

8. The integrated circuit co-layout method according to claim 1, wherein The allocating the macro module and the standard cell to different chips of the three-dimensional stacked structure includes: Allocating the macro cell to the top chip of the three-dimensional stacked structure; Allocating the standard cell to the bottom chip.

9. An integrated circuit co-layout device, characterized in that, including: A construction module for selecting a wire network model based on the wire network connection relationship and constructing a matrix and a force vector for quadratic programming layout based on the wire network model; An initial layout solution generation module for solving for the position of each cell according to the matrix and the force vector to obtain an initial cell layout solution; A batch processing module for performing overlapping optimization operations on standard cells and macro cells respectively to generate a legalized layout solution; A repulsive force simulation module for using the legalized layout solution as an anchor point and adding it to the wire network model to simulate the repulsive force between cells; An iteration control module for repeatedly calling the construction module, the initial layout solution generation module, the batch processing module, and the repulsive force simulation module until the wire length converges to obtain a final layout solution; An allocation module for allocating macro modules and standard cells to different chips of a three-dimensional stacked structure according to the final layout solution.

10. An electronic device, characterized in that, including: At least one processor; And a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute: the integrated circuit co-layout method according to any one of claims 1-8.

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