3D sensing circuit, sensing, storage and calculation integrated macro-cell circuit, system and data processing method

Abstract

The invention discloses a 3D sensing circuit, a sensing, storage and calculation integrated macro-cell circuit, a system and a data processing method, and the 3D sensing circuit comprises a 3D light signal sensing unit which is used for converting light flight time into a time pulse signal; the time conversion analog circuit is used for converting the flight time of the photons into analog current signals or analog voltage signals according to the time pulse signals; the time conversion analog circuit comprises a control module, an integration module and a reading module, and the control module is used for controlling the integration starting and ending of the integration module, outputting a starting signal when photons are emitted, and outputting a stopping signal when time pulse signals are received; the integration module is used for carrying out integration on the current after receiving the initial signal and ending the integration after receiving the stop signal; and the read-out module is used for converting the integral signal into a voltage signal and a current signal required by a system post-stage.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits and signal processing, and in particular to a 3D sensing circuit, a sensing-storage-computing integrated macro unit circuit, a system and a data processing method. Background Art

[0002] With the development of the industrial Internet, higher requirements are placed on video acquisition and processing technology. In traditional visual application systems, image sensors collect image information, convert optical signals into electrical signals, and convert them into digital signals after digital-to-analog conversion. The image data is then processed by the image signal processing unit, and finally output to the processor in the system through a special video interface, which then performs data analysis and makes corresponding controls and operations. In recent years, distance measurement sensors have become increasingly popular. Compared with the 2D image information of traditional image sensors, distance measurement sensors can provide distance information, which is called 3D information. The mainstream implementation methods include using APD devices and SPAD devices, and using light flight time TOF (Time OfFlight) to obtain more accurate distance information.

[0003] In applications such as image processing and laser ranging, Figure 1 As shown, the sensing, storage and computing integrated chip realizes efficient and low-power data processing by integrating sensing, storage and computing functions. Among them, in the middle is the processing macro unit (PE) 1 array, which is closely arranged together in the form of an array of PEs, such as a 1024*1024 scale. Because each PE includes a sensing, storage and computing basic unit, all PEs in the PE array can process the data in each unit in parallel at the same time. This method is also often called single instruction multiple data mode, namely SIMD, which is more common in GPUs. Row control modules 5 and column control modules 6 are designed in the horizontal and vertical directions of the PE array respectively. The row control module 5 is used to select rows and perform related control on the PE array. The corresponding column mode control module is used to select columns and perform related control on the PE array, as well as data readout selection. The periphery of the PE array also includes a peripheral digital module 4, an INS bus 41, a peripheral analog module 3, and an interface module 7.

[0004] like Figure 2 As shown, the PE unit includes a sensing unit (SU). The original signal can come from the detection of the SU, and then the SU can store and calculate, convert the analog signal into a digital signal, and then store it. For the visual perception unit, SU is divided into 2D and 3D. The optical signal of the 3D perception unit can be detected using an APD (avalanche photodiode) device or a SPAD (single photon avalanche diode) device. First, the transmitter needs to emit a laser, and the receiving SU measures the time from the emission to the return of the optical signal through APD or SPAD to calculate the distance of the object.

[0005] like Figure 3 As shown in the figure, the traditional TOF (time of flight) chip distance measurement principle usually uses SPAD and TDC (time to digital converter) to achieve accurate distance information measurement, in which the high-precision TDC (time todigital converter) circuit acts as a timer and a stopwatch. The TDC is synchronized with the time of the transmitter, and the optical signal received by the SPAD can generate current within picoseconds (ps) and be detected and recorded by the TDC. The TCSPC (Time Correlated Single Photon Counting) technology divides the time axis into several time intervals according to accuracy. Whenever the sensor pixel detects a single photon event, a digital pulse will be generated. At the same time, the time when the digital pulse is generated is recorded, and then the single photon count accumulated value in the corresponding time interval is "added by one". After a large number of repeated measurements, a lot of time data will be obtained, and these time data will be accumulated in the corresponding time interval in the same way, so that the corresponding single photon count histogram can be obtained.

[0006] Traditional Disadvantages:

[0007] The design of TDC is to calculate the flight time of light, the speed of light is 3×10 8 Meters / second, high-precision distance parameters require high-frequency clocks to achieve, which places great demands on both the process and the circuit. In order to obtain a highly stable TDC, the circuit is relatively complex, so the circuit area will also occupy a large area. The mainstream method of using TCSPC to calculate the distance result requires a large-capacity SRAM to store histogram information, so the efficiency is low. Summary of the invention

[0008] The present invention proposes a 3D sensing circuit, a sensing-storage-computing integrated macro unit circuit, a system and a data processing method, which can convert the flight time of light into a corresponding voltage or current signal, transmit it to the subsequent analog domain storage and computing unit, and perform distance information statistics and further application calculations.

[0009] The present invention provides a 3D sensing circuit, comprising:

[0010] A 3D optical signal sensing unit, used to convert the light flight time into a time pulse signal;

[0011] A time conversion analog circuit converts the flight time of photons into an analog current signal or an analog voltage signal according to a time pulse signal;

[0012] The time conversion analog circuit comprises: a control module, an integration module and a readout module.

[0013] The control module is used to control the start and end integration of the integration module, and is used to output a start signal when a photon is emitted, and output a stop signal when a time pulse signal is received;

[0014] An integration module, used to start integrating the current after receiving a start signal and to end the integration after receiving a stop signal;

[0015] The readout module is used to convert the integrated signal into the voltage signal and current signal required by the subsequent stage of the system.

[0016] Optionally, the integration module includes:

[0017] A reset switch is used to reset the integration module after an integration cycle, with its input terminal connected to a reset signal and its control terminal connected to a system reset signal;

[0018] An integrating capacitor, a first end of which is connected to the output end of the reset switch, and a second end of which is grounded;

[0019] The integral input circuit is composed of a current source and an integral switch. The input end of the integral switch is connected to the current source, the output end is connected to the first end of the integral capacitor, and the control end is connected to the output of the trigger.

[0020] Optionally, the control module is an RS trigger, whose R terminal is connected to the output of the pulse modulation unit and inputs a time pulse signal; the S terminal is connected to a system reset signal; and the Q terminal is connected to the control terminal of the integral switch.

[0021] Optionally, the control module is a latch, whose CK terminal is connected to the output of the pulse modulation unit and inputs a time pulse signal; the S terminal is connected to a system reset signal; the D terminal is grounded; and the Q terminal is connected to the control terminal of the integral switch.

[0022] Optionally, a logic circuit is also connected between the integration input circuit and the RS trigger or latch, and the logic circuit includes a NOR gate, wherein the first input terminal of the NOR gate is connected to the Q terminal of the RS trigger or latch, the second input terminal inputs a system reset signal, and the output terminal is connected to the control terminal of the integration switch.

[0023] Optionally, the readout module comprises:

[0024] A readout MOS tube, the gate of which is connected to the first end of the integrating capacitor, and the drain of which is grounded;

[0025] The drain of the MOS transistor is connected to the source of the readout MOS transistor, the gate is connected to the strobe control signal, and the source is connected to the output terminal.

[0026] Optionally, the readout module comprises:

[0027] The gate of the readout MOS tube is connected to the first end of the integrating capacitor, and the source is connected to a high level;

[0028] The drain of the MOS transistor is connected to the drain of the readout MOS transistor, the gate is connected to the strobe control signal, and the source is connected to the output end.

[0029] Optionally, the 3D optical signal sensing unit includes a SPAD module and an inverter connected to an output end of the SPAD module.

[0030] Optionally, the 3D optical signal sensing unit includes an APD module and a comparator connected to the APD module, wherein a positive segment thereof is connected to an output of the APD module, and a negative end thereof inputs a modulation signal.

[0031] Optionally, the reset switch and the integral switch MOS tube have a control end as a gate, an input end as a source, and an output end as a drain.

[0032] Optionally, a 2D optical signal sensing unit is further included, and an output end of the 2D optical signal sensing unit and an output end of the 3D optical signal sensing unit are commonly connected to a gate of the output MOS tube.

[0033] Optionally, the source of the output MOS tube is grounded, and the drain outputs current.

[0034] Optionally, the source of the output MOS tube is connected to VDD, and the drain outputs the voltage.

[0035] A hybrid sensing circuit with integrated sensing, storage and computing macro-unit circuit.

[0036] A sensing, storage and computing integrated circuit system.

[0037] A data processing method.

[0038] The present invention can convert the flight time of light into a corresponding voltage or current signal, which is convenient for the subsequent storage and computing unit to store and process the perception signal, and realize a 3D sensing and computing unit. While the execution efficiency is increased, the power consumption is very small. The processing application of 3D distance information is greatly flexible and rich. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 It is a schematic diagram of the architecture of a sensing, storage and computing integrated circuit system;

[0041] Figure 2 It is a schematic diagram of the architecture of a sensing, storage and computing integrated macro unit circuit;

[0042] Figure 3 is a schematic diagram of an existing 3D sensing circuit;

[0043] Figure 4 is a diagram of a 3D sensing circuit architecture according to an embodiment of the present invention;

[0044] Figure 5a is a schematic diagram of a 3D sensing circuit according to a first embodiment of the present invention;

[0045] Figure 5b is a schematic diagram of the working principle of the 3D sensing circuit of the first embodiment of the present invention;

[0046] Figure 6 is a schematic diagram of a 3D sensing circuit according to a second embodiment of the present invention;

[0047] Figure 7 is a schematic diagram of a 3D sensing circuit according to a third embodiment of the present invention;

[0048] Figure 8 is a schematic diagram of a 3D sensing circuit according to a fourth embodiment of the present invention;

[0049] Fig. 9 is a schematic diagram of a 3D sensing circuit according to another embodiment of the present invention. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more explicit definition of the protection scope of the present invention. Obviously, the embodiments described in the present invention are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0051] In this application, the use of "or" means "and / or" unless otherwise stated. Furthermore, the use of the term "comprising" and other forms such as "including" and "comprising" are not limiting. In addition, unless specifically stated otherwise, terms such as "element" or "component" encompass both elements and components comprising one unit and elements and components comprising more than one unit.

[0052] The present invention provides a sensing storage and computing integrated macro unit system, such as Figure 1As shown, in this embodiment, the sensing-storage-computing integrated macro unit circuit is specifically designed in a pixel-level sensing-storage-computing integrated chip, with a processing macro unit (PE) array in the middle. The PEs are closely arranged together in an array form, for example, a 1024*1024 scale. The internal structure of the PE is described in detail with reference to the specific embodiments of the sensing-storage-computing integrated macro unit circuit and the 3D sensing circuit later. Here, only the overall architecture of the sensing-storage integrated macro unit system is described.

[0053] Because each PE includes a sensing, storage and computing basic unit, all PEs in the PE array can process the data in each unit in parallel at the same time. Row control modules and column control modules are designed in the horizontal and vertical directions of the PE array respectively. The row control module is used to select rows and perform related control on the PE array, and the corresponding column mode control module is used to select columns and perform related control on the PE array, as well as data readout selection. Therefore, in addition to the PE array, the sensing and storage integrated circuit system also includes an analog-to-digital conversion unit (ADC) 2, a peripheral analog module 3, a peripheral digital module 4, a row control module 5, a column control module 6, an interface module 7, etc., and an INS bus 41 arranged on the periphery of the PE array.

[0054] The present invention also provides a sensing, storage and computing integrated macro unit circuit of a distance measurement sensor, such as Figure 2 As shown, in the present invention, PE includes a 3D perception (SU) unit, or a 2D, 3D hybrid perception unit. A communication interface between adjacent PEs, the adjacent PE communication unit Adjacent IF, is also designed in PE, which can provide the information of the 8 PEs surrounding the current PE to the current PE. The above-mentioned module units are connected together through a specially designed iSC bus sensor computing bus (iSC Sensor Computing Bus), and the analog signal can be a voltage or a current signal. In addition to the iSC bus, a global instruction bus INS bus is also designed in PE to perform overall operation control on each functional module in PE. Because the INS bus of each PE is controlled by the same global signal, the sensor computing system integration is achieved in this way. In PE, signal acquisition and calculation are all in the form of current.

[0055] The sensing circuit therein is described in detail below in combination with the above-mentioned sensing-storage-computing integrated macro unit system and sensing-storage-computing integrated macro unit circuit.

[0056] like Figure 4 As shown, in one embodiment of the present invention, the 3D sensing circuit includes: a 3D light signal sensing unit 301, which is used to convert the light flight time into a time pulse signal; a time conversion analog circuit (TAC Time to analog converter) 303, which converts the flight time of the photon into an analog current signal or an analog voltage signal according to the time pulse signal.

[0057] The time conversion analog circuit 303 includes: a control module, an integration module and a readout module, wherein the control module is used to control the start integration and the end integration of the integration module, and is used to output a start signal when a photon is emitted, and output a stop signal when a time pulse signal is received; the integration module is used to start integrating the current after receiving the start signal, and to end the integration after receiving the stop signal; the readout module is used to convert the integration signal into a voltage signal and a current signal required by the later stage of the system.

[0058] In one embodiment, if Figure 5a As shown, the 3D optical signal sensing unit 301 includes a SPAD module, specifically including a single photon avalanche diode and a quenching circuit (Quenching); the pulse modulation unit includes an inverter.

[0059] The control module is an RS trigger RS1, whose R terminal is connected to the output of the 3D light signal sensing unit, and inputs a time pulse signal sp, which is used as an integration end control signal; the S terminal is connected to the system reset signal st, which is used as an integration start control signal; the Q terminal is connected to the integration switch M int control terminal.

[0060] The integration module includes: a reset switch M rx , used to adjust the integral module C after one integration cycle. sig To reset, its input terminal is connected to the reset signal reset voltage, and the control terminal is connected to the system reset signal st; the integral capacitor C sig , whose first terminal is connected to the reset switch M int The output terminal of the circuit is grounded; the integral input circuit consists of a current source I int and integral switch M int Composition, integral switch M int The input terminal is connected to a current source I int , the output terminal is connected to the integrating capacitor C sig The first end of the control end is connected to the output of the RS trigger.

[0061] A logic circuit is also connected between the integral input circuit and the RS trigger. The logic circuit includes a NOR gate U1. The first input terminal of the NOR gate U1 is connected to the Q terminal of the RS trigger, the second input terminal inputs the system reset signal st, and the output terminal is connected to the integral switch M. int control terminal.

[0062] The readout module includes: a readout MOS tube M rd , its gate is connected to the integrating capacitor C sig The first end of the MOS tube M sel , its drain is connected to the readout MOS tube M rxThe source of the reset switch M is connected to the gate of the gate control signal SEL, and the source is connected to the output terminal to output the voltage signal to the MSC bus. rx And integral switch MOS tube M int , the control end is the gate, the input end is the source, and the output end is the drain.

[0063] In this embodiment, the RS flip-flop includes two NOR gates, and the relationship between the ports is as follows:

[0064] S terminal = 1, R terminal = 1, Q terminal = 0;

[0065] S terminal = 1, R terminal = 0, Q terminal = 1;

[0066] S terminal = 0, R terminal = 1, Q terminal = 0;

[0067] S = 0, R = 0, Q remains in the last storage state

[0068] The following is a further explanation of the working principle. Figure 5b The working principle is divided into four stages: initialization stage p1, flight stage p2, trigger stage p3, and hold stage p4.

[0069] 1. Initialization phase:

[0070] st=1,sp=0,Q=1

[0071] M int Shutdown, M rx On, C sig The voltage is reset to the reset voltage V reset .

[0072] The SPAD is reset and in charging state. The recharge photosensitivity state enters Geiger mode, ready to detect photons. At the same time, the TAC is reset.

[0073] 2. Flight phase:

[0074] st=0,sp=0,Q=x

[0075] M int On, M rx Shutdown, C sig Charge begins to accumulate, SPAD is in the detection state, and the voltage increases linearly with time. When the initial stage enters the flight stage, that is, when st changes from 1 to 0, the system controls the light emitting end to emit a light signal.

[0076] 3. Triggering phase:

[0077] When the initial stage enters the flight stage, that is, when st changes from 1 to 0, the system controls the light emitting end to send out a light signal. When the photon is detected by the SPAD and generates an avalanche current, the trigger signal sp is activated and becomes 1.

[0078] st=0,sp=1,Q=0

[0079] M int Shutdown, M rx Shutdown, C sig The voltage V=I*T (I is the current, T is the time from photon emission to detection).

[0080] 4. Maintaining stage:

[0081] st=0,sp=0,Q=0

[0082] M in Shutdown, M rx Shutdown

[0083] Keep C sig The voltage on the MOSFET remains unchanged until the next measurement cycle.

[0084] Thus, the readout MOS tube M of the subsequent stage is used rd A voltage is formed at the gate end, and the gate is controlled to control the on-current of the readout MOS tube, that is, the signal is converted into a current signal. This current signal can be connected to the iSC (in Sensor Computing) bus in the PE. It is further processed by other components connected to the MSC bus, such as performing operations on analog registers, or storing operations on digital registers, or passing it to adjacent PEs through Adjacent IF. In this embodiment, TAC is a conversion of time signals to analog signals. Unlike TDC (time to digital converter) in traditional SPADs, TAC does not convert time information into a binary digital signal, but converts time into an analog signal, such as a voltage signal or a current signal. The first method proposed by the present invention is TCC (time to current converter), which converts the light flight time into an analog signal such as a current, and then performs relevant processing in the PE to realize the integrated sensing, storage and computing of 3D.

[0085] Traditional DTOF chips require the SPAD device to be designed with an on-chip TDC to convert time into digital signals, and then send these signals to the system's processing chip. This is inefficient, the ranging accuracy is highly dependent on the operating frequency of the TDC, the power consumption is high, and the efficiency is low. The mainstream TCSPC method calculates the distance result, which requires a large-capacity SRAM to store histogram information, occupies chip area, and the power consumption is difficult to control.

[0086] The present invention can convert the flight time of light into a corresponding voltage or current signal, which is convenient for the subsequent storage and computing unit to store and process the perception signal, and realize a 3D sensing and computing unit. While the execution efficiency is increased, the power consumption is very small. The processing application of 3D distance information is greatly flexible and rich.

[0087] like Figure 6 As shown, in the second embodiment of the present invention, a voltage-type TAC, namely TVC (time to voltage converter), is adopted, that is, the signal is converted into a voltage signal for output.

[0088] The 3D optical signal sensing unit includes a SPAD module, specifically including a single photon avalanche diode, a quenching circuit (Quenching), and an inverter.

[0089] The control module is an RS trigger RS1, whose R terminal is connected to the output of the inverter and inputs the time pulse signal sp; the S terminal is connected to the system reset signal st; the Q terminal is connected to the integral switch M int The module is used to control the start and end integration of the integration module, and is used to output a start signal when a photon is emitted, and output a stop signal when a time pulse signal is received.

[0090] The integration module includes: a reset switch M rx , used to adjust the integral module C after one integration cycle. sig To reset, its input terminal is connected to the reset signal reset voltage, and the control terminal is connected to the system reset signal st; the integral capacitor C sig , whose first terminal is connected to the reset switch M int The output terminal of the circuit is grounded; the integral input circuit consists of a current source I int and integral switch M int Composition, integral switch M int The input terminal is connected to a current source I int , the output terminal is connected to the integrating capacitor C sig The first end of the control end is connected to the output of the RS trigger.

[0091] A logic circuit is also connected between the integral input circuit and the RS trigger. The logic circuit includes a NOR gate U1. The first input terminal of the NOR gate U1 is connected to the Q terminal of the RS trigger, the second input terminal inputs the system reset signal st, and the output terminal is connected to the integral switch M. int control terminal.

[0092] The difference from the above embodiment is that:

[0093] The readout module includes: a readout MOS tube M rd, its gate is connected to the integrating capacitor C sig The first end of the source is connected to a high level; the MOS tube M is selected sel , its drain is connected to the readout MOS tube M rd The drain of the device is connected to the gate of the device, the gate of the device is connected to the selection control signal SEL, and the source of the device is connected to the output terminal.

[0094] like Figure 7 As shown, in the third embodiment of the present invention, the 3D optical signal sensing unit includes a SPAD module, specifically including a single photon avalanche diode and a quenching circuit (Quenching) and an inverter connected to the output end of the SPAD module.

[0095] The integration module includes: a reset switch M rx , used to adjust the integral module C after one integration cycle. sig To reset, its input terminal is connected to the reset signal reset voltage, and the control terminal is connected to the system reset signal st; the integral capacitor C sig , whose first terminal is connected to the reset switch M int The output terminal of the circuit is grounded; the integral input circuit consists of a current source I int and integral switch M int Composition, integral switch M int The input terminal is connected to a current source I int , the output terminal is connected to the integrating capacitor C sig The first end of the control end is connected to the output of the latch LATCH.

[0096] A logic circuit is also connected between the integral input circuit and the latch LATCH. The logic circuit includes a NOR gate U1. The first input terminal of the NOR gate U1 is connected to the Q terminal of the latch LATCH, the second input terminal inputs the system reset signal st, and the output terminal is connected to the integral switch M int control terminal.

[0097] The readout module includes: a readout MOS tube M rd , its gate is connected to the first end of the integrating capacitor Csig, and its drain is grounded; the MOS tube M is selected sel , its drain is connected to the readout MOS tube M rx The source of the reset switch M is connected to the gate of the gate control signal SEL, and the source is connected to the output terminal to output the voltage signal to the iSC bus. rx And integral switch MOS tube M int , the control end is the gate, the input end is the source, and the output end is the drain.

[0098] The control module is a latch LATCH, whose CK terminal is connected to the output of the pulse modulation unit and inputs the time pulse signal sp; the S terminal is connected to the system reset signal; the D terminal is grounded; and the Q terminal is connected to the control terminal of the integral switch.

[0099] like Figure 8 As shown, in the fourth embodiment of the present invention, the 3D optical signal sensing unit includes an APD module, which specifically includes a photodiode APD and a bias circuit BIAS; and a comparator OP connected to the APD module, whose positive segment is connected to the output of the APD module and whose negative end inputs a modulated signal.

[0100] like Fig. 9 As shown, the present invention also proposes a 3D sensing circuit, which includes the above-mentioned 3D light signal sensing unit and also includes a 2D light signal sensing unit PD, the output end of the 2D light signal sensing unit and the output end of the 3D light signal sensing unit are connected to the gate of the output MOS tube M1, the source of the output MOS tube M1 is grounded, and the drain outputs a current I pix .

[0101] In another embodiment, the source of the output MOS tube M1 is connected to VDD, and the drain outputs voltage.

[0102] The present invention also proposes a data processing method using the above 3D sensing circuit.

[0103] The present invention proposes a new circuit principle and structure to realize the detection and perception of distance information of specific scenes. In addition to obtaining a 3D image with a certain resolution, the 3D perception circuit designed by the present invention is organically combined with the previously designed sensing-storage-computing macro unit to realize the 3D sensing-storage-computing circuit, which is directly budgeted and processed in the analog signal domain, greatly improving the delay, power consumption and efficiency.

[0104] The 3D sensing, storage and computing structure proposed in the present invention can provide methods and circuit support for subsequent 3D processing, such as edge extraction, feature point extraction and tracking of 3D information.

[0105] This design proposes a new structure and principle to realize the detection and perception of distance information. In addition to obtaining a 3D information map with a certain resolution, it cooperates with the processing unit to realize the application calculation of distance information and realize 3D related sensing, storage and computing applications. The characteristics of the present invention are small area and high ranging efficiency.

[0106] The 3D distance information sensing, storage and computing implementation method of the present invention breaks the implementation method of the traditional von Neumann architecture, and integrates single-chip 3D perception and signal processing into one more efficient execution.

[0107] The above descriptions are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structural or equivalent process transformations made using the contents of the specification and drawings of the present application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A 3D sensing circuit, characterized in that: include: A 3D optical signal sensing unit, used to convert the light flight time into a time pulse signal; A time conversion analog circuit converts the flight time of photons into an analog current signal or an analog voltage signal according to a time pulse signal; The time conversion analog circuit comprises: a control module, an integration module and a readout module. The control module is used to control the start and end integration of the integration module, and is used to output a start signal when a photon is emitted, and output a stop signal when a time pulse signal is received; An integration module, used to start integrating the current after receiving a start signal and to end the integration after receiving a stop signal; The readout module is used to convert the integrated signal into the voltage signal and current signal required by the subsequent stage of the system.

2. The 3D sensing circuit according to claim 1, characterized in that: The integration module comprises: A reset switch is used to reset the integration module after an integration cycle, with its input terminal connected to a reset signal and its control terminal connected to a system reset signal; An integrating capacitor, a first end of which is connected to the output end of the reset switch, and a second end of which is grounded; The integral input circuit is composed of a current source and an integral switch. The input end of the integral switch is connected to the current source, the output end is connected to the first end of the integral capacitor, and the control end is connected to the output of the trigger.

3. The 3D sensing circuit according to claim 2, characterized in that: The control module is an RS trigger, whose R terminal is connected to the output of the pulse modulation unit and inputs a time pulse signal; the S terminal is connected to the system reset signal; and the Q terminal is connected to the control terminal of the integral switch.

4. The 3D sensing circuit according to claim 2, characterized in that: The control module is a latch, whose CK terminal is connected to the output of the pulse modulation unit and inputs a time pulse signal; the S terminal is connected to the system reset signal; the D terminal is grounded; and the Q terminal is connected to the control terminal of the integral switch.

5. The 3D sensing circuit according to claim 3 or 4, characterized in that: A logic circuit is also connected between the integration input circuit and the RS trigger or latch, and the logic circuit includes a NOR gate, a first input terminal of the NOR gate is connected to the Q terminal of the RS trigger or latch, a second input terminal inputs a system reset signal, and an output terminal is connected to the control terminal of the integration switch.

6. The 3D sensing circuit according to claim 5, characterized in that: The readout module comprises: A readout MOS tube, the gate of which is connected to the first end of the integrating capacitor, and the drain of which is grounded; The drain of the MOS transistor is connected to the source of the readout MOS transistor, and the gate is connected to the strobe control signal. The source is connected to the output terminal.

7. The 3D sensing circuit according to claim 5, characterized in that: The readout module comprises: The gate of the readout MOS tube is connected to the first end of the integrating capacitor, and the source is connected to a high level; The drain of the MOS transistor is connected to the drain of the readout MOS transistor, and the gate is connected to the strobe control signal. The source is connected to the output terminal.

8. The 3D sensing circuit according to claim 6 or 7, characterized in that: The 3D optical signal sensing unit includes a SPAD module and an inverter connected to the output end of the SPAD module.

9. The 3D sensing circuit according to claim 6 or 7, characterized in that: The 3D optical signal sensing unit includes an APD module and a comparator connected to the APD module, a positive segment of which is connected to the output of the APD module, and a negative end of which inputs a modulation signal.

10. The 3D sensing circuit according to claim 9, characterized in that: The reset switch and the integral switch MOS tube have a control end as a gate, an input end as a source, and an output end as a drain.

11. The 3D sensing circuit according to claim 1, characterized in that: It also includes a 2D optical signal sensing unit, and the output end of the 2D optical signal sensing unit and the output end of the 3D optical signal sensing unit are commonly connected to the gate of the output MOS tube.

12. The 3D sensing circuit according to claim 11, characterized in that: The source of the output MOS tube is grounded, and the drain outputs current.

13. The 3D sensing circuit according to claim 11, characterized in that: The source of the output MOS tube is connected to VDD, and the drain outputs the voltage.

14. A sensing-storage-computing integrated macro unit circuit comprising the 3D sensing circuit according to any one of claims 1 to 13.

15. A sensing-storage-computing integrated circuit system comprising the sensing-storage-computing integrated macro unit circuit of claim 14.

16. A data processing method using the 3D sensing circuit according to any one of claims 1-13.

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