Voltage drop violation repairing method

Abstract

The embodiment of the invention provides a voltage drop violation repairing method, and relates to the technical field of integrated circuit design. The method comprises the following steps of: adjusting unit positions according to a logical relationship between units and a time sequence trend, and reducing the density of the units in a local region; output pins of the macro-cells face the interior of the core area of the chip, and the macro-cells are placed outside the boundary of the core area and are additionally provided with isolation areas; adding a checkerboard-shaped power supply network to the area occupied by all the units, so that each unit is connected to a power supply; placing the first standard unit close to the boundary of the whole area close to the second standard unit according to the logic relation and the time sequence trend between the standard units; the number of the decoupling units is increased according to a preset leakage power consumption threshold value, and the decoupling units are placed at intervals according to a preset interval threshold value; through combined use and combined action of the steps, voltage drop is weakened or eliminated.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a voltage drop violation repair method. Background Art

[0002] IR, IR drop, I refers to current, R refers to resistance, and IR drop is voltage drop, which refers to a phenomenon in which the voltage drops or rises in the power supply and ground network in the circuit. In advanced processes, the width of metal lines is getting narrower and narrower, which causes its resistance value to rise. When the logic gate units on a metal line flip at the same time, it will cause a large voltage drop fluctuation. The voltage drop also depends on the size of the equivalent resistance from the power PAD to the calculated logic gate unit. The PAD is the solder joint, and the metal connection is made when the chip is packaged. IR drop is divided into static IR drop and dynamic IRdrop, that is, static voltage drop and dynamic voltage drop.

[0003] The publication number is CN113609626A, and its name is a method for repairing voltage drop violations and related devices. It provides a method to repair the voltage drop problem by first reducing the size of the acquired network to be repaired to obtain a reduced-size network, and finally inserting a decoupling unit into the reduced-size network to obtain a repaired network, thereby avoiding the problem of serious congestion caused by too many signal lines Signal Net. PrimeTime is used to perform timing repair on the decoupling processing network to obtain a Timing ECO script, and then the IR problem is handled through the script. The PrimeTime is a tool used by Sysnopsys for timing analysis. However, the technical solution relies on a single scenario, cannot deal with a variety of complex violations, cannot effectively reduce voltage drops from more aspects, and cannot deal with a variety of complex and difficult-to-handle voltage drop problems.

[0004] Therefore, how to solve the voltage drop has become a technical problem that needs to be solved urgently. Summary of the invention

[0005] The invention provides a voltage drop violation repair method to solve the technical problem of voltage drop.

[0006] In order to solve the above technical problems, the technical solutions adopted by the present invention are as follows:

[0007] A voltage drop violation repair method comprises the following steps:

[0008] Step S1: When the cell density in the local area is greater than a preset density threshold, the cell positions are adjusted according to the logical relationship and timing trend between the cells to reduce the cell density in the local area;

[0009] Step S2: Direct the output pins of the macrocell toward the inside of the core area of ​​the chip, place the macrocell outside the boundary of the core area, leave a complete core area for placing standard cells, and add an isolation area around the macrocell;

[0010] Step S3: adding a checkerboard-shaped power network to the area occupied by all units so that each unit can be connected to the power supply;

[0011] Step S4: when the distance between the first standard cell and the second standard cell having a logical relationship is greater than a preset distance, adjusting the positions of the standard cells according to the logical relationship and timing trend between the standard cells, placing the first standard cell close to the boundary of the overall area close to the second standard cell;

[0012] Step S5: increasing the number of decoupling units according to a preset leakage power consumption threshold, and placing the decoupling units at intervals according to a preset interval threshold.

[0013] A further technical solution is: in step S1, when the cell density in the local area is greater than a preset density threshold and less than twice the preset density threshold, the cell position is manually adjusted, and the preset density threshold is 1; when the cell density in the local area is greater than or equal to twice the preset density threshold, the cell position is adjusted through a script control tool.

[0014] A further technical solution is that in step S1, the step of manually adjusting the unit position includes manually selecting and adjusting the unit position, taking the flying wires connecting the units as the logical relationship between the units, taking the direction of the flying wires as the timing direction between the units, and confirming the placement position.

[0015] A further technical solution is that: in step S1, the step of adjusting the unit position by using a script control tool includes:

[0016] Determine the type of unit according to the hierarchical structure, and create a group of units through the ICC2 command create_rp_group, so that the unit density in the local area after the grouping is processed is less than the preset density;

[0017] Based on the logical relationship between the units, add each type of unit to the corresponding group through the ICC2 command add_to_rp_group;

[0018] Create constraint boundaries based on the logical relationship between cells through the ICC2 command create_bound;

[0019] Automatically place cells via the ICC2 command place_opt;

[0020] Use the ICC2 command check_legality to check whether there is any overlap in the placement of units;

[0021] The ICC2 is a tool for digital circuit layout and routing.

[0022] A further technical solution is that: in the step S2, each macro unit is placed according to a preset distance threshold between macro units, so that the distance between macro units is greater than the preset distance threshold between macro units.

[0023] A further technical solution is: in the step S3, a checkerboard-shaped power supply network is added through ICC2 commands create_pg_std_cell_conn_parttern, set_pg_strategy, and compile_pg, and the ICC2 is a tool for digital circuit layout and routing.

[0024] A further technical solution is that: in step S4, the value range of the preset distance is greater than or equal to the height value of two standard units and less than or equal to the height value of three standard units, the flying line connecting the first standard unit and the second standard unit is used as the logical relationship between the standard units, the direction of the flying line between the first standard unit and the second standard unit is used as the timing direction between the standard units, the step of adjusting the position of the standard unit is to manually select the standard unit and move it, and the placement position of the first standard unit is located in the area near the flying line between the standard units.

[0025] A further technical solution is that: in the step S5, when the leakage power consumption is greater than a preset leakage power consumption threshold, the number of added decoupling units does not exceed half of the number of original decoupling units.

[0026] The beneficial effects of adopting the above technical solution are:

[0027] A method for repairing a voltage drop violation includes the following steps: adjusting the cell position according to the logical relationship and timing trend between cells to reduce the cell density in the local area; the output pins of the macro cells are oriented toward the inside of the core area of ​​the chip, and the macro cells are placed outside the boundary of the core area and an isolation area is added; a checkerboard-shaped power supply network is added to the area occupied by all cells to connect each cell to the power supply; according to the logical relationship and timing trend between standard cells, the first standard cell close to the boundary of the overall area is placed close to the second standard cell; the number of decoupling cells is increased according to a preset leakage power consumption threshold, and the decoupling cells are placed at intervals according to a preset interval threshold. The voltage drop is weakened or eliminated by the combined use and joint action of the above steps.

[0028] Step S1 is used to solve the technical problem of voltage drop caused by the simultaneous inversion of many cells due to the excessively high cell density in the local area; Step S2 is used to solve the technical problem of voltage drop caused by unreasonable global layout planning floorplan; Step S3 is used to solve the technical problem of voltage drop caused by uneven power supply due to unreasonable global power planning powerplan; Step S4 is used to solve the technical problem of static voltage drop caused by voltage division of metal wires in the power supply network; Step S5 is used to solve the technical problem of dynamic voltage drop caused by current fluctuation when the power supply switches in the logic circuit.

[0029] Based on the combination of step S1 and step S3, when the units with logical relationship are placed far away, the farther units are placed as close as possible according to the timing and logic, thereby forming step S4. Under the joint action, the technical problem of static voltage drop is solved, and the static voltage drop is weakened or eliminated.

[0030] Based on step S1, the number of decoupling units is increased, thereby forming step S5. Under the joint action, the technical problem of dynamic voltage drop is solved, and the dynamic voltage drop is weakened or eliminated.

[0031] Please refer to the detailed description of the specific implementation method. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 4 is a flow chart of a voltage drop violation repair method provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] In addition, the term "and / or" in this article is only a description of the association relationship between the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0035] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application can also be implemented in other ways different from those described herein, and those skilled in the art can make similar generalizations without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0036] The purpose of this application is to provide a means to effectively solve the IR drop violation problem, which can more efficiently solve the IR drop problem in various complex situations after digital back-end layout and routing.

[0037] STA, Static Timing Analysis, is a process in chip back-end design, which usually analyzes the timing path of the designed circuit.

[0038] ECO, Engineering Change Order, refers to the process in which designers make small adjustments to the circuit and standard cell layout in the later stage of design based on problems exposed in static timing analysis and post-simulation. They make small-scale optimizations while keeping the original design layout and routing results basically unchanged, repair the remaining violations of the chip, and ultimately meet the chip sign-off standards.

[0039] Decap, decap cell, decoupling unit, in order to avoid the influence of IR drop on circuit performance, a capacitor composed of MOS tube is usually placed between the power supply and the ground line. This capacitor is called a decoupling capacitor or decoupling unit. Its function is to supplement current to the circuit when the transient current increases and the voltage drops to keep the voltage between the power supply and the ground line stable, and prevent the voltage drop of the power line and the increase of the ground line voltage.

[0040] After completing the steps of layout planning, layout planning, clock tree synthesis and routing, the physical implementation of the chip design has been basically determined. Next, it is necessary to perform STA, ECO repair timing, perform physical inspection, and finally perform IR inspection and repair the exposed violations.

[0041] Voltage drop analysis process:

[0042] After the layout and routing is completed, the final design data needs to be analyzed for voltage drop to ensure that the design works in a stable power supply environment. The voltage drop analysis process has the following steps:

[0043] The first step is to prepare the data for voltage drop analysis. The data that needs to be prepared before voltage drop analysis include gate-level netlist, timing constraint file sdc, parasitic parameter information file spef and physical information file lef.

[0044] The second step is to set up the power grid library. The power grid library ploc is the basic data extracted from the cell library for power consumption calculation.

[0045] The third step is power consumption calculation. The above data is imported into Redhawk, a unique power consumption calculation tool of Synopsys. The tool will simulate accurate static voltage drop and dynamic voltage drop according to different design requirements and actual scale.

[0046] The fourth step is voltage drop analysis. Voltage drop analysis needs to be judged based on the report generated by Redhawk. The judgment criteria are generally: static power consumption needs to be controlled within 3% to 5% of the operating voltage, and dynamic power consumption needs to be controlled within 15% of the operating voltage.

[0047] IR, voltage drop occurs for several reasons:

[0048] Reason 1: The cell density in a local area is too high, causing many cells to reverse at the same time, resulting in voltage drop.

[0049] Reason 2: The global floorplan is unreasonable, the macro layout does not take IR drop into consideration, and the macro placement does not leave space for the decoupling unit.

[0050] Cause 3: The global power planning powerplan is unreasonable and the power supply is uneven.

[0051] Reason 4: The main reason for the static voltage drop phenomenon is the voltage division of the metal wires in the power supply network, that is, the voltage division caused by the resistance of the metal wires themselves.

[0052] Reason 5: The main reason for the dynamic voltage drop phenomenon is the voltage drop caused by the current fluctuation when the power supply switches in the logic circuit.

[0053] The technical solution of the present application will analyze the voltage drop situations that occur in various occasions, and use a variety of methods to solve the voltage drop problem more comprehensively and efficiently.

[0054] After place and routing, STA and PV need to be repaired. PV is physical verification, which is the abbreviation of physical verify. Then EMIR is checked. EM needs to check two items: power EM and signal EM; IR needs to check two items: static IR and dynamic IR. This technical solution repairs IR through multiple methods, which can deal with violations of multiple voltage drops and save time for design violation repair.

[0055] like Figure 1 As shown, the present invention discloses a voltage drop violation repair method comprising the following steps:

[0056] There are five corresponding repair methods for the five causes of IR drop:

[0057] Step S1: For reason 1, the local unit density is too high. It is necessary to break up the densely placed units manually or with tools. The principle of breaking up should be based on the logical relationship and timing trend between the units.

[0058] According to the calculation of ICC2 tool, when the density ratio map_data is greater than 1, it is a high-density area, and twice the preset density is 2, which is a severe high-density area.

[0059] When the number of high-density units is small, that is, when the unit density in the local area is greater than the preset density threshold and less than twice the preset density threshold, the preset density threshold is 1. It is more efficient to manually break up the units. Through ICC2, a product of Synopsys, the operation interface command controls the selection of units, and manually breaks up the selected units to start moving. The placement is confirmed by the flying wires connecting the units. It is more appropriate to select a position roughly in the middle of the connection between the unit and other units. Of course, this also depends on whether there is a gap to move.

[0060] The flying wires between units reflect the logical connection relationship between the units. They are usually placed manually based on experience and judged by the flying wires. It is advisable to select the middle of two logically related units so that the units at both ends of the flying wires can be affected.

[0061] IR problems occur between cells and between cells and standard cells.

[0062] The unit includes basic unit, standard unit and macro unit. The unit is the most basic delay unit. For example, an ordinary register, buffer, inverter, etc. are all basic units. The standard unit is a highly equal unit customized by the factory. Macro unit is a broad concept, which is divided into hard core and soft core. Hard core is IP such as memory, latch PLL, etc. used to read and store data. Soft core is a macro unit containing sub-levels, and the internal structure cannot be seen. Macro unit is generally an independent IP, belonging to three types of delay devices.

[0063] The basic units include inverters, AND gates, registers, selectors, full adders, etc. These units can adopt different sizes and driving capabilities according to design requirements to adapt to the optimization between performance, area, power consumption and cost.

[0064] Standard cells are pre-designed, tested and functional logic blocks in integrated circuit design. They are stored in a database so that designers can call them according to circuit design requirements. Standard cells usually have equal-height rectangular shapes, and their sizes are integer multiples of the basic size or minimum size to ensure the regularity and efficiency of circuit design. The design of standard cells takes into account the use of automatic layout and routing tools, including the location, size and shape of the input and output ports to meet the grid spacing requirements to improve the efficiency of the router. In addition, the design of standard cells also includes special design rules, such as all cells are equal-height rectangles, or the height is an integer multiple of the basic height, and the power and ground lines are generally located at the upper and lower boundaries of the cell to facilitate connection sharing and reduce chip area.

[0065] When the number of high-density units is huge, that is, when the local area unit density is greater than or equal to twice the preset density threshold, it is necessary to use the script control tool to implement it: determine the unit type according to the hierarchical structure, create a relatively empty placement group through the ICC2 command create_rp_group, add each type of unit to the corresponding group through the ICC2 command add_to_rp_group; create a constraint boundary through the ICC2 command create_bound, and automatically place the unit through the ICC2 command place_opt; check whether there is any overlap in the unit placement through the ICC2 command check_legality. This process relies on specific scripts to execute and implement.

[0066] The ICC2 is a tool used by Synopsys to place and route digital circuits, and the placement group is a tool for grouping unit placement.

[0067] Step S2: For reason 2, the unreasonable global floorplan design, this needs to be based on the report generated by Redhawk. Generally speaking, static IR drop exceeding 3% to 5% of the operating voltage and dynamic IR drop exceeding 15% of the operating voltage are unreasonable. Exceeding this limit may cause the chip to cause logic errors or stop working because it cannot obtain the required voltage. So in the case of unreasonable floorplan, a good floorplan is very important for the later stage of design. Rules for floorplan placement: For example, the macro unit pin should be oriented toward the inside of the chip core area to facilitate routing and timing optimization; avoid narrow channels between macro units, too narrow channels will cause violations of routing, timing and DRC; place macro units as close to the boundary as possible, leaving a complete core area for standard units; and add isolation areas around macro units to avoid violating foundry design rules.

[0068] The DRC is the design rule check, which is the abbreviation of design rule check.

[0069] Each macro unit is placed according to a preset distance threshold between macro units, so that the distance between macro units is greater than the preset distance threshold between macro units, and narrow channels are avoided between macro units. The distance threshold between macro units is 10um to 15um.

[0070] The UMC28nm process is generally suitable for a distance of 10um to 15um, and the distance threshold between macro units is adjusted accordingly according to different process designs.

[0071] During the layout stage, when there are many macro units, they are first placed automatically by the tool. You can add constraints to the tool to define the distance between the macro units. The tool will only place the macro units based on this distance.

[0072] When there are fewer macro units, they are usually placed manually, and engineers sometimes ignore this limit value. The appropriate distance can be defined based on physical inspection violations that occur later.

[0073] Step S3: For reason 3, the unreasonable layout of powerplan, without affecting the winding resources, the density and layout of the power network are enhanced according to different design requirements to enhance the power supply capacity of the power ground; the ICC2 commands create_pg_std_cell_conn_parttern, set_pg_strategy, and compile_pg are used to add a checkerboard-shaped power network to the design. This allows the current density to be evenly distributed to avoid electromigration effects. Proper power planning is also very important for subsequent power consumption analysis and voltage drop analysis, and can avoid risks in advance.

[0074] Step S4: For reason 4, the main reason for the static voltage drop phenomenon is the voltage division of the metal wires of the power network, that is, the voltage division of the metal wires' own resistance. Regarding the voltage division of the metal wires of the power network, you can refer to step S3 to enhance the power supply capacity of the power grid; if the units with logical relationships are placed relatively far apart, the connection between them will become longer, which will cause uneven voltage division of the long metal wires' own resistance, and then lead to voltage drop. This problem can be referred to step S1. Relatively far units can also be placed closer according to timing and logic by manual or tool, that is, when the distance between the first standard unit and the second standard unit with logical relationship is greater than the preset distance, the first standard unit close to the boundary of the overall area will be placed close to the second standard unit according to the timing trend and logical relationship.

[0075] The preset distance is a height value of two standard units, or a height value of three standard units, or a value between the height value of two standard units and the height value of three standard units.

[0076] The flying wire connecting the first standard cell and the second standard cell is used as the logical relationship between the standard cells, and the direction of the flying wire between the first standard cell and the second standard cell is used as the timing direction between the standard cells. The step of adjusting the position of the standard cell is to manually select the standard cell and move it. The placement position of the first standard cell is located in the area near the flying wire between the standard cells, that is, it is preferably moved between the first standard cell and the second standard cell.

[0077] According to experience, if a flying line connects two, three or four standard cells, the standard cell with a serious voltage drop can be moved to a position slightly farther away from the other standard cells according to the flying line, and finally the distance from the other standard cells is similar, which will not affect the timing problem. Generally, it is appropriate to place it at a distance of three to four rows, otherwise it will affect the timing problem.

[0078] row: The horizontal grid where standard cells are placed. The height of the row is the height of the standard cell.

[0079] Step S5: For reason 5, the main reason for the dynamic voltage drop phenomenon is the voltage drop caused by the current fluctuation when the power supply switches the logic circuit. This problem can refer to step S1, and the number of decoupling units can be increased in the seriously affected area to eliminate the voltage drop, that is, the decoupling units are placed according to the preset interval threshold, the preset interval threshold is 100um, and when the leakage power consumption is greater than the leakage power consumption threshold, the number of added decoupling units shall not exceed half of the number of original decoupling units.

[0080] The leakage power consumption threshold is selected based on the following conditions, which are based on the report generated by the power consumption analysis tool Redhawk. Generally speaking, the static power consumption is within 3% to 5% of the operating voltage, and the dynamic power consumption is controlled within 15% of the operating voltage.

[0081] The design requirements for chips of different sizes and processes are different. Generally speaking, a column is placed every 100um in the layout, and the ICC2 command create_stdcell_fillers is used to control the tool to automatically add. Of course, adding too many decoupling cells will increase the leakage power consumption of the chip. The specific number needs to be defined based on the specific project analysis. Or in places where power consumption is more serious, it is okay to place half of the original number.

[0082] This application discloses a variety of methods to repair IR drop. After layout and routing, engineers need to perform physical verification, static timing analysis, and then check and repair IR drop. The causes of static IR drop and dynamic IR drop are: local cell density is too high, global floorplan layout is unreasonable, powerplan layout is unreasonable, etc. This application proposes to manually or script to break up cells in local high density areas, add sufficiently uniform decoupling cells, enhance powerplan PG mesh, and reasonably layout floorplan, etc. These solutions can broaden engineers' ideas for solving problems and increase engineers' efficiency in solving problems.

[0083] Compared with the prior art, the advantages of the present application are that it is more comprehensive, more effective, and more targeted in solving various voltage drop violation problems that have occurred.

[0084] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution disclosed in the present invention can be achieved, and this document does not limit this.

[0085] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A voltage drop violation repair method, characterized in that: The following steps are included: Step S1: When the cell density in the local area is greater than a preset density threshold, the cell positions are adjusted according to the logical relationship and timing trend between the cells to reduce the cell density in the local area; Step S2: Direct the output pins of the macrocell toward the inside of the core area of ​​the chip, place the macrocell outside the boundary of the core area, leave a complete core area for placing standard cells, and add an isolation area around the macrocell; Step S3: adding a checkerboard-shaped power network to the area occupied by all units so that each unit can be connected to the power supply; Step S4: when the distance between the first standard cell and the second standard cell having a logical relationship is greater than a preset distance, adjusting the positions of the standard cells according to the logical relationship and timing trend between the standard cells, placing the first standard cell close to the boundary of the overall area close to the second standard cell; Step S5: increasing the number of decoupling units according to a preset leakage power consumption threshold, and placing the decoupling units at intervals according to a preset interval threshold.

2. The voltage drop violation repair method according to claim 1, wherein: In step S1, when the cell density in the local area is greater than a preset density threshold and less than twice the preset density threshold, the cell position is manually adjusted, and the preset density threshold is 1; when the cell density in the local area is greater than or equal to twice the preset density threshold, the cell position is adjusted through a script control tool.

3. The voltage drop violation repair method according to claim 2, wherein: In step S1, the step of manually adjusting the unit position includes manually selecting and adjusting the unit position, taking the flying wires connecting the units as the logical relationship between the units, taking the direction of the flying wires as the timing direction between the units, and confirming the placement position.

4. The voltage drop violation repair method according to claim 2, wherein: In step S1, the step of adjusting the unit position by using the script control tool includes: Determine the type of unit according to the hierarchical structure, and create a group of units through the ICC2 command create_rp_group, so that the unit density in the local area after the grouping is processed is less than the preset density; Based on the logical relationship between the units, add each type of unit to the corresponding group through the ICC2 command add_to_rp_group; Create constraint boundaries based on the logical relationship between cells through the I CC2 command create_bound; Automatically place cells via the ICC2 command place_opt; Use the ICC2 command check_legality to check whether there is any overlap in the placement of units; The ICC2 is a tool for digital circuit layout and routing.

5. The voltage drop violation repair method according to claim 1, wherein: In the step S2, each macro unit is arranged according to a preset distance threshold between macro units, so that the distance between macro units is greater than the preset distance threshold between macro units.

6. The voltage drop violation repair method according to claim 1, wherein: In the step S3, a checkerboard-shaped power supply network is added through ICC2 commands create_pg_std_cell_conn_parttern, set_pg_strategy, and compile_pg, and the ICC2 is a tool for digital circuit layout and routing.

7. The voltage drop violation repair method according to claim 1, wherein: In step S4, the value range of the preset distance is greater than or equal to the height value of two standard units and less than or equal to the height value of three standard units, the flying line connecting the first standard unit and the second standard unit is used as the logical relationship between the standard units, and the direction of the flying line between the first standard unit and the second standard unit is used as the timing direction between the standard units. The step of adjusting the position of the standard unit is to manually select the standard unit and move it, and the placement position of the first standard unit is located in the area near the flying line between the standard units.

8. The voltage drop violation repair method according to claim 1, wherein: In step S5, when the leakage power consumption is greater than a preset leakage power consumption threshold, the number of added decoupling units does not exceed half of the number of original decoupling units.

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