Macro-cell layout evaluation optimization method based on large language model

Abstract

The invention provides a macro-cell layout evaluation optimization method based on a large language model, and belongs to the field of electronic design automation. According to the method, a large language model is introduced to assist layout generation, a current initial layout is improved in combination with connection weight analysis, on the other hand, an improved result is judged and continuously iterated according to natural language feedback of an experience manual or an expert, and closed-loop optimization is formed; carrying out weight quantization on direct and indirect signal paths among macro units, constructing a logic association strength matrix, and realizing accurate identification and priority ranking of key time sequence paths; the availability score of each candidate layout scheme is calculated through a layout availability scoring module, dynamic measurement is carried out on surrounding standard unit resources, the resource distribution state is evaluated in real time, the position of a macro unit is actively adjusted, and resource congestion or waste is avoided; the method is deeply integrated with an open source EDA tool, the dependence on a commercial tool is reduced, the tool chain deployment and iteration period is shortened, and the transportability and usability of the method are guaranteed.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic design automation (EDA), and in particular to a macro cell layout evaluation and optimization method based on a large language model for integrated circuits. Background Art

[0002] As the scale and complexity of systems-on-chip (SoCs) continue to rise, the number of macrocells included in chip designs has grown exponentially, from a few in the early days to hundreds or even thousands today. The physical placement of macrocells directly impacts core metrics such as signal transmission path length, timing closure quality, and power consumption and area (PPA), becoming a critical factor limiting chip performance and yield. In practice, macrocell placement is often performed as a one-time, static operation, generating placement plans through netlist clustering, heat map analysis, or one-time, rule-of-thumbnail layouts. This approach lacks the ability to proactively respond to issues revealed during subsequent verification phases.

[0003] Traditional macrocell layout methods rely primarily on black-box optimization techniques such as simulated annealing, particle swarm optimization, and genetic algorithms, or mathematical programming strategies based on analytical engines (such as DREAMPlace), as well as recently emerging data-driven models such as reinforcement learning and the Transformer scheduler. While these methods can achieve some success in the initial layout phase, the entire optimization process is encapsulated within the algorithm. Weight allocation, constraint relaxation, and convergence strategies are opaque to designers, making it impossible to provide traceable decision-making evidence and difficult to adjust core parameters on demand, resulting in a serious "black-box" problem.

[0004] More significantly, existing tools lack the ability to incrementally iterate and optimize generated layouts. Once subsequent timing analysis reveals violations, prominent congestion hotspots, or defects in manufacturability verification, the only options are to rerun the entire process or rely on manual fine-tuning. Rerunning the entire process not only takes hours to days, but also introduces new layout deviations by repeatedly importing the same initial data. Manual fine-tuning is inefficient and, lacking a systematic feedback mechanism, often struggles to converge to the optimal solution, severely limiting design cycles and iteration frequency.

[0005] At the same time, subjective design intent and engineers' extensive experience cannot be systematically integrated into the automated layout process. Chip design often requires manual retention or constraints for factors such as critical paths, safety margins, and process characteristics. However, current layout tools cannot dynamically inject these preferences at runtime, resulting in a disconnect between automated strategies and actual needs. Optimization results differ significantly from design expectations, forcing designers to compensate through repeated verification and adjustments later.

[0006] Furthermore, mainstream EDA software often evaluates idle standard cell resources based on overall available area or coarse-grained placement rectangles, lacking quantitative analysis of dynamic availability metrics such as maximum connected block size, local resource connectivity, and convex hull compactness. After macrocell placement, idle resources often exhibit either concentrated hotspots or excessive dispersion, posing significant challenges for subsequent clock tree synthesis, routing congestion optimization, and parasitic capacitance correction, further limiting the potential for realizing a chip's PPA.

[0007] Given these shortcomings, a new macrocell layout optimization framework is urgently needed: First, it must ensure transparency and visibility into the layout decision-making process, enabling designers to understand algorithm weight allocations and iteration paths in real time and participate in optimization. Second, it must support incremental iterative optimization based on the existing layout, eliminating the need to rerun the entire system from scratch. Furthermore, it must flexibly integrate subjective design intent with engineer feedback, embedding human inputs such as critical path constraints, safety margins, and process preferences into the optimization loop. Furthermore, it must provide real-time measurement and feedback on resource placement based on a dual quantitative evaluation of multi-hop signal connectivity weights and the dynamic availability (connectivity and compactness) of standard cells. By building a transparent, closed-loop, and adaptive optimization system, deep collaborative optimization of logical interconnect and physical resources can be achieved, effectively improving the low latency, high bandwidth, and rapid iteration capabilities of high-performance SoC designs. Summary of the Invention

[0008] In order to solve the problems existing in the prior art, the present invention proposes a macro cell layout evaluation and optimization method based on a large language model, introduces a large language model-assisted connection weight analysis combined with a layout availability score, and drives the intelligent prompt word Prompt to achieve a dual evaluation of the macro cell logical relevance and physical environment. Subsequently, under the guidance of the combined weight and scoring results, candidate layout plans are automatically generated, and subsequent tree synthesis CTS, routing and other steps are completed through interface calls with mainstream EDA tools (such as OpenROAD). Finally, the layout strategy is dynamically adjusted in an iterative closed loop, significantly reducing manual parameter adjustment and the number of iterations, and improving PPA performance. This collaborative optimization model provides a new paradigm for the automation of next-generation SoC macro cell layouts.

[0009] The technical solutions of the present invention are as follows:

[0010] A macrocell layout evaluation and optimization method based on a large language model is characterized by:

[0011] (1) Obtaining macrocell layout information and netlist data of the current chip design, and converting the macrocell layout information into a structured data file;

[0012] (2) Connection weight analysis, calculating the connection weight matrix between macro units, specifically including:

[0013] First, the network analyzes the signal types, transmission directions, and topological relationships between macrocells in the netlist. Then, based on the preset signal type priority and physical distance attenuation strategy, initial weights are assigned to directly connected and multi-level transmission paths, and the weights of all paths are accumulated and normalized. Finally, a matrix describing the strength of the macrocell logical connections, namely the connection weight matrix, is output.

[0014] (3) Large Language Model (LLM) driven layout optimization;

[0015] Based on the connection weight matrix and the current layout information, a prompt word is constructed and the LLM is called to understand the signal strength distribution and the current layout constraints at the semantic level. The LLM outputs preliminary optimized macro unit position adjustment suggestions, generates candidate layout solutions, returns the layout macro coordinates, and updates the current layout information. During the iterative process, the LLM not only generates candidate layouts but also integrates natural language feedback from expert experience manuals or manual input to achieve intelligent reasoning and improvement of layout strategies.

[0016] (4) layout usability score;

[0017] For each candidate layout solution provided by LLM, the layout availability scoring module dynamically measures the surrounding standard cell resources, including: scanning the free cell areas in the candidate layout; using grid or graph algorithms to identify and mark macro cell coordinates, calculating basic metrics, and obtaining the availability score of each candidate layout solution through the layout availability scoring formula. This score is used as part of the next layout optimization iteration prompt of LLM in step (3), providing feedback for subsequent LLM iterations.

[0018] (5) Iterative determination and final layout output;

[0019] The large language model compares the availability scores of candidate layout solutions and combines LLM / manual layout modification suggestions to determine the current optimal layout. Specifically, when the score reaches the optimal level of the current layout or there is no significant improvement after multiple rounds of iterations, the current layout is determined to be the optimal solution and exported as a script file adapted to open source EDA tools to complete the final generation of automated layout data. If the score does not meet the standard, the modification suggestions are output and returned to step (3), starting the next round of closed-loop iteration until convergence.

[0020] (6) EDA tool verification;

[0021] The EDA tool is automatically called to perform clock tree synthesis, place and route, static timing and congestion analysis, design rule checking, and layout and netlist consistency checking on the exported layout script. The key indicators output by the EDA tool are extracted and input into the large language model together with the usability score and layout target results for comparison as the basis for the final convergence judgment. If all indicators meet the predetermined threshold, the layout optimization is declared complete; otherwise, return to step (3) and continue to iterate to improve the layout quality.

[0022] Furthermore, the step (2) specifically includes the following steps:

[0023] First, read the complete netlist file, parse all macro unit (Macro) instances, ports and network node information, and build the netlist data structure in memory;

[0024] Secondly, according to the netlist data structure, the macro unit ports contained in each net are traversed to identify the direct connection relationship between all macro unit pairs, and the signal name, port direction and attribute labels such as clock, data signal or control signal are recorded;

[0025] Then, for each identified macro cell, an initial weight is applied according to the type of signal it carries: the clock signal is given the highest priority type weight, and the data signal and control signal are given the second highest and medium weights respectively;

[0026] Then, the specific total connection weight matrix is ​​calculated according to the following predetermined weight conversion formula: W AB The specific formula is as follows:

[0027] The total connection weight calculation formula is:

[0028] W AB =W direct +W indirect

[0029] The direct connection weight calculation formula is:

[0030]

[0031] Where S(A,B) is the set of directly connected signals between macro units A and B, and W type (s) is the signal type weight, W dir (s) is the signal direction type weight;

[0032] The indirect connection weight calculation formula is:

[0033]

[0034] Where P(A,B) is the set of all indirect connection paths from macrocell A to macrocell B, |p| is the number of hops in the path, and s i is the i-th signal on the path;

[0035] Finally, the processed macro-cell connection weight matrix is ​​output as a quantitative basis for subsequent layout optimization and evaluation, guiding the generation of layout optimization solutions.

[0036] Furthermore, the step (4) specifically includes the following steps:

[0037] First, the layout availability scoring module scans and reads the layout coordinate information of the current macro unit to determine the specific location of the macro unit in the current layout;

[0038] Secondly, the layout availability scoring module performs grid or graph modeling on the current layout, identifies all standard cell locations not occupied by macro cells, and marks them as idle nodes, forming an idle resource distribution map.

[0039] Then, based on the actual situation of the macrocell layout, a basic metric is calculated to evaluate the connectivity and density of the standard cell area around each macrocell; the basic metric includes the maximum connected area of ​​the available standard cell area The total usable area of ​​a standard unit (A usable_SC ), and the convex hull area of ​​the standard cell area (A convex_hull_SC ).

[0040] Next, substitute the basic metrics into the layout usability scoring formula, which is:

[0041]

[0042] In the formula, the parameter λ is a weight factor used to balance the proportion of layout connectivity and compactness; among them, the first term Measures the connectivity of the standard unit area, the second Measures the compactness of the layout area;

[0043] Finally, the layout usability score is output as part of the prompt for the next iteration of the LLM.

[0044] Furthermore, the specific steps of step (6) are as follows:

[0045] First, the exported final layout script is used to call the Clock Tree Synthesis (CTS) module of the EDA tool to perform fan-out balancing, buffer insertion, and netlist constraint verification on the global or partitioned clock network, generate the final clock topology, and output a CTS report.

[0046] Secondly, Placement & Routing is performed based on the CTS results, calling the detailed routing engine to complete the physical placement adjustment and signal connection of macro cells and standard cells to form a complete physical layout;

[0047] Next, we run static timing analysis (STA) and congestion assessment to measure the worst negative delay (WNS) and total negative delay (TNS) of critical paths, and calculate the connection density and potential congestion hotspots in each area.

[0048] Subsequently, the design rule check (DRC) and layout and netlist consistency check (LVS) are performed in sequence to verify the compliance of the layout manufacturing rules and the consistency of the physical layout and the logical netlist, and to capture possible violations or connectivity differences;

[0049] Finally, all evaluation results of CTS, routing, timing, congestion, and DRC / LVS are summarized to generate a structured report. If all key indicators meet the preset thresholds, the final layout is confirmed. Otherwise, the key information in the report is fed back to the layout optimization driven by the large language model (LLM) in step (3), triggering the next round of iterative optimization to ensure continuous improvement in the performance of the macrocell layout.

[0050] The technical effects of the present invention are as follows:

[0051] (1) Introducing a large language model (LLM) to assist layout generation: combining connection weight analysis to improve the current initial layout, and relying on experience manuals or natural language feedback from experts to judge the improvement results and continuously iterate, forming a closed-loop optimization; compared with traditional layout methods, it reduces reliance on manual experience and improves layout diversity and feasibility.

[0052] (2) Multi-hop signal connection weight analysis: Quantify the weights of direct and indirect (multi-hop) signal paths between macro units, integrate signal type, direction, and hop attenuation factors, and construct a logical association strength matrix; achieve accurate identification and priority sorting of key timing paths, reduce the risk of timing violations, and improve timing closure efficiency.

[0053] (3) Dynamic layout availability scoring: Based on indicators such as the maximum connected block area of ​​idle standard cells, convex hull compactness, and total available area, an availability scoring function is constructed; after each round of iteration, the resource distribution status is evaluated in real time, and the macro cell position is actively adjusted to avoid resource congestion or waste, and to optimize wiring congestion and parasitic capacitance distribution.

[0054] (4) Deep integration of open source EDA tools: Through automatically generated Tcl / JSON scripts, the system can interface with open source tools such as OpenROAD to achieve one-click scheduling of the entire process of clock tree synthesis, layout and routing, timing analysis, and DRC. This reduces dependence on commercial tools, shortens tool chain deployment and iteration cycles, and ensures the portability and ease of use of the method. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 This is an overall flow chart of the macrocell layout evaluation and optimization method based on a large language model of the present invention;

[0056] Figure 2 This is a specific flow chart of the connection weight analysis in the method of the present invention;

[0057] Figure 3 A specific flow chart for scoring layout usability in the method of the present invention;

[0058] Figure 4 This is a flow chart for verification using EDA tools in the method of the present invention. DETAILED DESCRIPTION

[0059] The following is combined with Figure 1 To the attached Figure 4 This paper describes in detail the macrocell layout evaluation and optimization method based on a large language model. This example uses a 28nm process SoC design as an example to describe the key implementation details of the present invention, including acquisition of existing layout information, connection weight analysis, layout availability scoring, large-model optimized macro placement, OpenROAD interface calls, and iterative verification. This is intended to facilitate understanding and application of the present invention by those skilled in the art, and does not limit the scope of protection of the present invention.

[0060] As attached Figure 1 As shown in the figure, the macrocell layout evaluation and optimization method based on the large language model of the present invention is process-driven and comprehensively covers closed-loop iterative optimization from initial data acquisition to final verification output. The entire process is divided into six main steps, combining the large language model (LLM) and open source EDA tools to achieve transparent, traceable, and incremental improvement of the macrocell physical layout. The specific steps include:

[0061] (1) Get the current layout information;

[0062] First, netlist data and existing macrocell layouts are read from the chip design environment. This includes macrocell geometry, the distribution of occupied standard cells, and the coordinates and shape information of the remaining available cell areas, as found in EDA files such as LEF / DEF. A preprocessing module then converts this heterogeneous macrocell layout data into a unified JSON format, generating a placement_raw.json file that serves as structured input for subsequent analysis and optimization. This step preserves the designer's manual adjustments while providing a standardized data foundation for the automated process.

[0063] (2) Connection weight analysis;

[0064] After completing the data formatting, the present invention starts the connection weight analyzer to quantitatively evaluate the direct connection and multi-hop signal paths between each pair of macro units. First, the signal types, signal transmission directions and topological relationships between macro units in the netlist are analyzed; then, according to the preset signal type priority and physical distance attenuation strategy, initial weights are assigned to the direct connection and multi-level transmission paths respectively; finally, all path weights are accumulated and normalized, and a matrix describing the logical association strength of the macro units is output. This matrix intuitively reflects the global macro unit signal interaction hotspots. After the matrix is ​​input into the large language model, the large model evaluates the connection priority between macro modules based on the matrix. For example, modules with high connection weights should be placed close to each other to reduce layout area and wiring resources, etc., providing accurate decision-making basis for the subsequent optimization stage.

[0065] (3) Large Language Model (LLM) driven layout optimization;

[0066] This paper introduces GPT-4o, an advanced large language model-assisted tool. Based on the connection weight matrix and current layout information, it constructs a prompt and calls the LLM. LLM uses the connection weight matrix to determine which modules are highly coupled and should be placed close together. It then semantically understands signal strength distribution and layout constraints, outputs preliminary optimized macro unit position adjustment suggestions, generates candidate layout solutions, returns layout macro coordinates, and updates the current layout information. During the iterative process, LLM not only generates candidate layouts but also integrates natural language feedback from expert experience manuals or manual input to achieve intelligent reasoning and improvement of layout strategies.

[0067] (4) layout usability score;

[0068] For each candidate layout solution provided by LLM, the present invention dynamically measures the surrounding standard cell resources through a layout availability scoring module. Specifically, it includes: scanning the free cell areas in the candidate layout; using a grid or graph algorithm to identify and mark the macro cell coordinates, calculating the maximum connected available area, the total available blank area, and the convex hull enclosed area, and then calculating the layout availability scoring formula to obtain the availability score of each candidate layout solution. This score quantitatively reflects the resource utilization efficiency and congestion risk, and is used as part of the next layout optimization iteration prompt of LLM in step (3), providing accurate feedback for subsequent LLM iterations.

[0069] (5) Iterative determination and final layout output;

[0070] The Large Language Model (LLM) compares candidate layout solutions and usability scores, and combines LLM / manual layout modification suggestions to determine the current optimal layout. Specifically, when the score reaches the optimal level (maximum score) or there is no significant improvement after multiple rounds of iterations, the current layout is determined to be the optimal solution, completing the final generation of automated layout data. If the score does not meet the standard, the modification suggestions are output and returned to step (3), starting the next round of closed-loop iteration until convergence.

[0071] (6) EDA tool verification;

[0072] Finally, the present invention automatically calls open source EDA tools such as OpenROAD, first converting the optimized macrocell layout coordinate data into a Tcl / JSON script (such as initial_macro_placement.tcl) that can be recognized by OpenROAD, and then executing clock tree synthesis (CTS), placement and routing (Placement & Routing), static timing and congestion analysis (STA & Congestion), and design rule checking (DRC / LVS) on the layout script in sequence. The key indicators output by the tool (such as WNS, TNS, congestion rate, power consumption, area, etc.) will be extracted and input into the large language model together with the availability score and layout target results for comparison as the basis for the final convergence judgment. If all indicators meet the predetermined threshold, the layout optimization is declared complete; otherwise, return to step (3) and continue to iterate to improve the layout quality.

[0073] Through the above six closely connected processes, the present invention realizes closed-loop optimization of the entire process from data acquisition, logic association quantification, intelligent layout generation, quantitative usability evaluation, to tool chain verification, taking into account both subjective design intent and data-driven analysis, and providing a transparent, efficient and controllable automated solution for high-performance SoC macro unit layout.

[0074] Figure 2The implementation process of the connection weight analysis in step (2) of the method of the present invention is shown. Specifically, the following steps are included:

[0075] First, the complete netlist file is read, all macro unit (Macro) instances, ports and network node information are parsed, and the netlist data structure is built in the memory to form the original connection list for subsequent analysis.

[0076] Secondly, according to the netlist data structure, traverse the macro unit ports contained in each net (Net), identify the direct connection relationship between all macro unit pairs, and record the signal name, port direction (input / output), and attribute labels such as clock, data signal or control signal.

[0077] Then, for each identified macro cell, an initial weight is applied according to the type of signal carried: the clock signal is given the highest priority type weight, and the data signal and control signal are given the second highest and medium weights respectively.

[0078] Then, the specific total connection weight matrix is ​​calculated according to the following predetermined weight conversion formula: W AB The specific formula is as follows:

[0079] The total connection weight calculation formula is:

[0080] W AB =W direct +W indirect

[0081] The direct connection weight calculation formula is:

[0082]

[0083] Where S(A,B) represents the set of directly connected signals between macro units A and B. Specifically, W type (s) is the signal type weight, which is assigned according to the signal type. For example, the clock signal has a higher weight, followed by data and control signals. W dir (s) is the signal direction type weight, which is assigned according to the signal direction. The weight of bidirectional signal is higher than that of unidirectional signal.

[0084] The indirect connection weight calculation formula is:

[0085]

[0086] Where P(A,B) represents the set of all indirect connection paths from macrocell A to macrocell B, |p| is the number of hops in the path, and s iis the i-th signal on the path. This formula calculates the indirect path weight by weighting on a hop-by-hop basis. The weight of the signal with more hops decreases gradually, ensuring that connections with shorter paths have higher priority.

[0087] Finally, the processed macro-cell connection weight matrix is ​​output as a quantitative basis for subsequent layout optimization and evaluation, guiding the generation of layout optimization solutions.

[0088] Figure 3 The implementation process of step (4) of the method of the present invention for layout usability scoring is shown, which specifically includes the following steps:

[0089] First, the layout availability scoring module scans and reads the layout coordinate information of the current macro unit to determine the specific position of the macro unit in the current layout.

[0090] Secondly, the layout availability scoring module performs grid or graph modeling on the current layout, identifies all standard cell locations not occupied by macro cells, and marks them as idle nodes to form an idle resource distribution map.

[0091] Then, based on the actual situation of macrocell layout, basic metrics are calculated to evaluate the connectivity and density of standard cell areas around each macrocell. The basic metrics include the maximum connected area of ​​the available standard cell area (A largest_connected_SC ), the total available area of ​​the standard unit (A usable_SC ), and the convex hull area of ​​the standard cell area (A convex_hull_SC ).

[0092] Next, substitute the basic metrics into the layout usability scoring formula, which is:

[0093]

[0094] In the formula, the parameter λ is a weight factor used to balance the proportion of layout connectivity and compactness, and the preset weight is 0.5. Measures the connectivity of the standard unit area, the second Measures the compactness of the layout area. By adjusting the value of λ, you can flexibly emphasize the connectivity or compactness of the layout according to design requirements.

[0095] Finally, the layout availability score is output as part of the next iterative prompt, guiding the LLM to make targeted optimization adjustments to the layout and guide the subsequent macro cell layout optimization and iteration process to achieve optimal physical resource utilization for the overall layout.

[0096] Figure 4 The implementation process of step (6) of the method of the present invention using EDA tools is shown. The specific implementation steps are as follows:

[0097] First, the optimized macrocell layout coordinate data is converted into a Tcl / JSON script recognizable by OpenROAD, ensuring that all command formats and attribute mappings are correct so that subsequent tool modules can be called smoothly.

[0098] Secondly, the OpenROAD Clock Tree Synthesis (CTS) module is called to perform fan-out balancing, buffer insertion, and netlist constraint verification on the global or partitioned clock network, generate the final clock topology, and output a CTS report.

[0099] Then, based on the CTS results, Placement & Routing is performed, and the detailed routing engine is called to complete the physical placement adjustment and signal connection of macro cells and standard cells to form a complete physical layout.

[0100] Next, run static timing analysis (STA) and congestion assessment to measure the worst negative delay (WNS) and total negative delay (TNS) of the critical path, and count the connection density and potential congestion hotspots in each area.

[0101] Subsequently, design rule checking (DRC) and layout and netlist consistency checking (LVS) are performed in sequence to verify the layout manufacturing rule compliance and the consistency of the physical layout with the logical netlist, catching possible violations or connectivity differences.

[0102] Finally, all evaluation results for CTS, routing, timing, congestion, and DRC / LVS are summarized to generate a structured report. If all key indicators meet the preset thresholds, the final layout is confirmed; otherwise, the key information in the report is fed back to step (3), triggering the next round of iterative optimization to ensure continuous improvement in macrocell layout performance.

[0103] Finally, it should be noted that the purpose of disclosing the embodiments is to facilitate a further understanding of the present invention. However, those skilled in the art will appreciate that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be determined by the scope defined in the claims.

Claims

1. A macrocell layout evaluation and optimization method based on a large language model, characterized in that: Specifically: (1) Obtaining macrocell layout information and netlist data of the current chip design, and converting the macrocell layout information into a structured data file; (2) Connection weight analysis, calculating the connection weight matrix between macro units, specifically including: First, the network analyzes the signal types, transmission directions, and topological relationships between macrocells in the netlist. Then, based on the preset signal type priority and physical distance attenuation strategy, initial weights are assigned to directly connected and multi-level transmission paths, and the weights of all paths are accumulated and normalized. Finally, a matrix describing the strength of the macrocell logical connections, namely the connection weight matrix, is output. (3) Large Language Model (LLM) driven layout optimization; Based on the connection weight matrix and the current layout information, a prompt word is constructed and the LLM is called to understand the signal strength distribution and the current layout constraints at the semantic level. The LLM outputs preliminary optimized macro unit position adjustment suggestions, generates candidate layout solutions, returns the layout macro coordinates, and updates the current layout information. During the iterative process, the LLM not only generates candidate layouts but also integrates natural language feedback from expert experience manuals or manual input to achieve intelligent reasoning and improvement of layout strategies. (4) layout usability score; For each candidate layout solution provided by LLM, the layout availability scoring module dynamically measures the surrounding standard cell resources, including: scanning the free cell areas in the candidate layout; using grid or graph algorithms to identify and mark macro cell coordinates, calculating basic metrics, and obtaining the availability score of each candidate layout solution through the layout availability scoring formula. This score is used as part of the next layout optimization iteration prompt of LLM in step (3), providing feedback for subsequent LLM iterations. (5) Iterative determination and final layout output; The large language model compares the availability scores of candidate layout solutions and combines LLM / manual layout modification suggestions to determine the current optimal layout. Specifically, when the score reaches the optimal level of the current layout or there is no significant improvement after multiple rounds of iterations, the current layout is determined to be the optimal solution and exported as a script file adapted to open source EDA tools to complete the final generation of automated layout data. If the score does not meet the standard, the modification suggestions are output and returned to step (3), starting the next round of closed-loop iteration until convergence. (6) EDA tool verification; The EDA tool is automatically called to perform clock tree synthesis, place and route, static timing and congestion analysis, design rule checking, and layout and netlist consistency checking on the exported layout script. The key indicators output by the EDA tool are extracted and input into the large language model together with the usability score and layout target results for comparison as the basis for the final convergence judgment. If all indicators meet the predetermined threshold, the layout optimization is declared complete; otherwise, return to step (3) and continue to iterate to improve the layout quality.

2. The method according to claim 1, wherein The step (2) specifically The following steps are involved: First, read the complete netlist file, parse all macrocell instances, ports, and network node information, and build the netlist data structure in memory; Secondly, according to the netlist data structure, the macro unit ports contained in each net are traversed to identify the direct connection relationship between all macro unit pairs, and the signal name, port direction and attribute labels such as clock, data signal or control signal are recorded; Then, for each identified macro cell, an initial weight is applied according to the type of signal it carries: the clock signal is given the highest priority type weight, and the data signal and control signal are given the second highest and medium weights respectively; Then, the specific total connection weight matrix is ​​calculated according to the following predetermined weight conversion formula: W AB The specific formula is as follows: The total connection weight calculation formula is: IN AB =In direct +W indirect The direct connection weight calculation formula is: Where S(A,B) is the set of directly connected signals between macro units A and B, and W type (s) is the signal type weight, W dir (s) is the signal direction type weight; The indirect connection weight calculation formula is: Where P(A,B) is the set of all indirect connection paths from macrocell A to macrocell B, |p| is the number of hops in the path, and s i is the i-th signal on the path; Finally, the processed macro-cell connection weight matrix is ​​output as a quantitative basis for subsequent layout optimization and evaluation, guiding the generation of layout optimization solutions.

3. The method according to claim 1, wherein The step (4) specifically includes the following steps: First, the layout availability scoring module scans and reads the layout coordinate information of the current macro unit to determine the specific location of the macro unit in the current layout; Secondly, the layout availability scoring module performs grid or graph modeling on the current layout, identifies all standard cell locations not occupied by macro cells, and marks them as idle nodes, forming an idle resource distribution map. Then, based on the actual situation of the macrocell layout, a basic metric is calculated to evaluate the connectivity and density of the standard cell area around each macrocell; the basic metric includes the maximum connected area of ​​the available standard cell area The total usable area of ​​a standard unit (A usable_SC ), and the convex hull area of ​​the standard cell area (A convex_hull_SC ). Next, substitute the basic metrics into the layout usability scoring formula, which is: In the formula, the parameter λ is a weight factor used to balance the proportion of layout connectivity and compactness; among them, the first term Measures the connectivity of the standard unit area, the second Measures the compactness of the layout area; Finally, the layout usability score is output as part of the prompt for the next iteration of the LLM.

4. The method according to claim 1, wherein The specific steps of step (6) are as follows: First, the clock tree synthesis (CTS) module of the EDA tool is called for the exported final layout script to perform fan-out balancing, buffer insertion, and netlist constraint verification on the global or partitioned clock network, generate the final clock topology, and output a CTS report. Secondly, Placement & Routing is performed based on the CTS results, calling the detailed routing engine to complete the physical placement adjustment and signal connection of macro cells and standard cells to form a complete physical layout; Next, we run static timing analysis (STA) and congestion assessment to measure the worst negative delay (WNS) and total negative delay (TNS) of the critical path, and calculate the connection density and potential congestion hotspots in each area. Subsequently, the design rule check (DRC) and the layout and netlist consistency check (LVS) are executed in sequence to verify the compliance of the layout manufacturing rules and the consistency of the physical layout and the logical netlist, and to capture possible violations or connectivity differences; Finally, all evaluation results of CTS, routing, timing, congestion, and DRC / LVS are summarized and a structured report is generated. If all key indicators meet the preset thresholds, the final layout is confirmed. Otherwise, the key information in the report is fed back to the layout optimization driven by the large language model (LLM) in step (3), triggering the next round of iterative optimization to ensure that the macro cell layout performance continues to improve.

5. The method according to claim 1 or 4, wherein: The EDA tool is OpenROAD.

6. The method according to claim 1, wherein The LLM tool is GPT-4o.

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