29 results about "Core Storage" patented technology

The invention belongs to the technical field of engineering cost, and discloses an engineering cost data security management system based on a block chain. The system is composed of an Internet of Things data acquisition and preprocessing module, a heterogeneous block chain core storage module, a dynamic consensus verification module, an intelligent contract and AI decision module, a multi-dimensional audit tracking module, a cross-chain authority management module and an intelligent early warning and decision support module. Data hierarchical storage is realized through a main chain-subchain-side chain three-level block chain architecture, key data is encrypted, a dynamic permission matrix of a cross-chain permission management module is matched, a whole-process security barrier from collection to interaction is constructed, data collected by an Internet of Things terminal is preprocessed to generate a non-tampering verification certificate, and the verification certificate is stored in a database. A dynamic consensus mechanism ensures compliance of uplink data, a multi-dimensional auditing module tracks an operation track in real time, data tampering and unauthorized access risks are eradicated from the technical level, and meanwhile the requirement of a data security law for sensitive information protection is met.

The invention discloses a DSP application deployment optimization method and system, a medium and a product, and the method comprises the steps: analyzing a to-be-deployed DSP application, extracting a directed acyclic graph, if operators in the directed acyclic graph are all in a support operator list of a target DSP chip, traversing the operators in the directed acyclic graph, and if the operators in the directed acyclic graph are all in the support operator list of the target DSP chip, determining that the operators in the directed acyclic graph are all in the support operator list of the target DSP chip; dividing the operators into intra-core storage operators and DDR (Double Data Rate) storage operators according to storage requirements of the operators and intra-core storage capacity of a target DSP (Digital Signal Processor) chip, and distributing and calculating the number of cores; storing configuration information of all operators in an end side model file; and deploying the end side model file of the to-be-deployed DSP application to the target DSP chip by using the deployment tool. The invention aims at solving the problem of low efficiency of the current DSP application deployment method by adaptively configuring the storage type and the calculation core number in the application deployment process, and realizing efficient and universal DSP application deployment optimization.

A storage device reduces power consumption and processes a first command in a low power mode. The storage device includes a controller to process host commands when the storage device is in a fully active state and to enter a deactivated state when the storage device enters the low power mode. An always-on processor on the storage device enters a sleep state when the storage device enters the low power mode. The always-on processor receives a notification of an incoming host command when the storage device is in the low power mode. When the always-on processor determines that the incoming command is a first command, the always-on processor processes the first command and remains in the sleep state. When the always-on processor determines the incoming command is a second command, the always-on processor may activate the controller to return the storage device to the fully active state.

The utility model belongs to the field of transformer part production, and discloses a single-frame iron core storage device which comprises a tray and a supporting piece fixedly arranged on the tray, three supporting faces evenly distributed in the circumferential direction of the tray are arranged on the supporting piece, and the included angle between any two adjacent supporting faces on a horizontal projection plane is 60 degrees. A limiting check block is fixedly arranged at the position, corresponding to the radial outer side of each supporting face, of the surface of the tray, and a clamping space used for containing the single-frame iron core is formed between each limiting check block and the corresponding supporting face; on the horizontal projection plane, the top edge of the supporting face is arranged close to the center of the tray, and the bottom edge of the supporting face is arranged close to the edge of the tray. According to the utility model, three single-frame iron cores with the same energy efficiency grade can be stably stored at one place; the centralized storage device is suitable for the transformer part production industry and used for centralized storage of the three single-frame iron cores before splicing.

The present application relates to the technical field of data processing, and especially relates to a sparse direct solution method based on data kernel external storage, which comprises the following steps: obtaining a coefficient matrix of a high-dimension sparse linear equation group, analyzing a non-zero element distribution mode and a matrix topological structure to establish a task dependency relationship; detecting a system memory capacity and a disk performance parameter to set a slice size parameter, dividing a wavefront matrix into data slices with balanced floating-point operation amounts to execute a left-looking numerical decomposition; creating a message queue and a monitoring mechanism to realize asynchronous disk storage; reading data from the disk to execute a numerical update cycle; and establishing a back substitution solution memory work area to generate a numerical solution by using a previous generation back substitution algorithm. The present application utilizes disk storage to relieve memory pressure and supports large-scale finite element simulation application.

Apparatuses and methods for an integrated device with trusted execution environment (TEE) confidential computing support are disclosed. An apparatus and method for extending IO device security protocols to an integrated processor. For example, an example processor package includes: a plurality of cores to execute instructions; an interconnect structure coupled to the plurality of cores; a memory interface circuit coupled to the interconnect structure, the memory interface circuit to couple the plurality of cores to one or more memories; a root complex comprising: a security circuit operable as a root of trust (RoT) and a bridge to the interconnect structure, the security circuit for establishing secure communications with one or more root complex integrated endpoint (RCiEP) devices integrated into the processor package; and a security protocol and data model (SPDM) engine of the security circuit for providing RCiEP encryption and SPDM protocol services to establish a secure communication channel with each RCiEP device.

The invention discloses a design method of an AI compiler of a multi-core end side AI chip, and belongs to the field of AI chip scheduling systems. According to the method, a multi-core storage allocation strategy, a synchronization mechanism and code generation optimization Pass are set in the compiling process, and efficient scheduling and modular management of the multi-core parallel computing tasks are achieved. The method is based on a multi-stage intermediate representation framework popular in the industry, corresponding functions are easy to develop, a multi-core storage distribution and synchronization mechanism can be defined in a specific Pass, modular management is achieved, the stability and expansibility of a compiler can be improved while the flexibility of a multi-core framework is guaranteed, and the method is suitable for popularization and application. Therefore, the performance and the development efficiency of the end-side AI chip in a complex application scene are improved.

Provided are a distributed parallel computing based graph computing method, a distributed parallel computing system and a computer readable medium. A graph computing method comprises: obtaining data of a graph to be computed, the graph comprising a plurality of vertices and edges; storing the graph according to a compressed sparse row format, and storing the graph in a sparse matrix form, wherein all adjacent edges having a same vertex are continuously stored, and an offset array is used to support an index function thereof; and for subgraphs in which the degrees of both source vertices and target vertices are greater than a predetermined threshold, in forward graphs, performing segmentation according to target vertices, i.e., the column of a matrix, and in reverse graphs, performing segmentation according to source vertices, i.e., the row of the matrix, and further dividing the subgraph into a plurality of segmented subgraph (SSG) components, so that a target vertex in each SSG is limited within a preset range. According to the SSG method of the embodiment for a high-degree vertex, the conventional problem that the space-time locality of accessing data of an adjacent vertex is poor due to a large vertex range of a single large graph is avoided or relieved.

A storage device reduces power consumption and processes a first command in a low power mode. The storage device includes a controller to process host commands when the storage device is in a fully active state and to enter a deactivated state when the storage device enters the low power mode. An always-on processor on the storage device enters a sleep state when the storage device enters the low power mode. The always-on processor receives a notification of an incoming host command when the storage device is in the low power mode. When the always-on processor determines that the incoming command is a first command, the always-on processor processes the first command and remains in the sleep state. When the always-on processor determines the incoming command is a second command, the always-on processor may activate the controller to return the storage device to the fully active state.

The application relates to the technical field of engineering geology exploration, and discloses a 3D scanning core characteristic parameter identification system and method, which comprises a core storage module and a 3D scanning module; the method comprises the following steps: separating complete and fragmented cores by self-adaptive cleaning and separation of drilling core samples, forming a space-attribute binding initial data set; dynamically adjusting the height and levelness of a 3D laser scanner by an automatic numerical control platform, generating an optimal scanning path topology network covering all core boxes; the scanning path topology network feeds back point cloud coverage in real time, dynamically adjusts the rotation angle, and outputs a full-angle high-density core point cloud sequence; the full-angle high-density core point cloud sequence is fused by multi-scale features, and an automatic columnar chart, a quantitative parameter set and a joint parameter package are generated. Through automatic and high-precision scanning and data analysis, the application realizes digitalized collection of cores and accurate calculation of geological parameters, and improves the efficiency and quality of geological exploration.

The application discloses a neural network load mapping method and device of a multi-core storage and computing integrated chip, and belongs to the field of artificial intelligence hardware acceleration and in-memory computing. The method extracts a matrix multiplication operator of a neural network and a data dependency relationship between the operators, obtains a neural network load directed computation graph, and then generates a storage and computing integrated chip load mapping result according to the neural network load directed computation graph and architecture parameters of the storage and computing integrated chip, and further generates a chip configuration program in combination with configuration register information in the chip architecture parameters, so as to realize automatic and efficient mapping of the neural network.

The utility model discloses a square silicon core stack frame relates to silicon core storage equipment technical field, including base, base bottom four corners all are rotatoryly connected with universal wheel, the base top is provided with a plurality of support frame, support frame outside is provided with elevating system, the base top is provided with auxiliary cooling mechanism. The utility model discloses a square silicon core stack frame, elevating system passes through the rotation handle and drives the rotation of worm, the rotation of screw rod is driven by worm wheel engagement, and fixed block and support frame are driven by screw sleeve and lift, and the synchronous adjustment of the height of each layer support frame is realized through the telescopic cooperation of articulated frame, adapts the storage demand of different size square silicon core, and convenient to take and put operation, improves the use convenience.

A process includes first operating an ECU to control operation of the powertrain system including executing by a processor a control operation using a first value of a first calibration stored in the nonvolatile core memory and a first run time value stored in a volatile core memory, receiving via an interface a tuning message including a tuning value directed to the first value of the first calibration parameter stored in the nonvolatile core memory, the tuning value differing from the first value, redirecting the tuning value to be stored in a volatile memory, and second operating the ECU to control operation of the powertrain system, the second operating including second executing by the processor the control operation using the tuning value stored in the volatile memory and a second run time value stored in the volatile core memory.

The invention provides a database storage link performance optimization method which can be applied to the technical field of computer system software performance optimization. The method comprises the steps of performing compression and reconstruction on an original instruction sequence of a structured query language parser in a database storage link based on instruction compression and expansion provided by a reduced instruction set processor platform, and generating an optimized instruction sequence with higher code density; based on a memory management attribute of a reduced instruction set processor platform and a layout control function of a compiling linker, performing aggregation layout optimization on a physical storage position of an instruction code of a core storage management function in a database storage link in a processor instruction cache; based on single-instruction multi-data stream extension provided by a reduced instruction set processor platform, key operations related to batch data access and processing in a database storage link execution process are converted from a scalar execution mode to a vectorization execution mode.

The invention discloses a high-throughput file processing system and method. The system comprises a client module, a metadata module, a storage cluster set and a system management module, the storage cluster set comprises a plurality of storage clusters, and each storage cluster comprises a cluster management unit, one or more storage service units and disks corresponding to the storage service units; the metadata module is used for storing file related information serving as a core storage engine; the system management module is used for determining a target storage cluster; the client module is used for realizing mounting of a local file system, determining a target storage service unit after receiving an IO request initiated by the file system, and sending the IO request to the target storage service unit; the storage service unit is used for acquiring data from the corresponding disk or writing the data into the corresponding disk; and the cluster management unit manages all the storage service units in the storage cluster. By means of the scheme, the file data read-write efficiency and the data storage reliability can be improved.

The present invention relates to a computation method for inferring a convolutional neural network implemented on a multi-core computing platform, each core comprising a local core memory of capacity 'Cm' and a computing unit, the cores being grouped into core groups, such that in a group, one core is assigned to the computations of neural operations and is connected via neighbor links to at least one immediate neighboring core.The method includes, during an inference, steps consisting of preloading a subset of operands required to perform a neural operation into the local core memories of the core groups, the local core memories of a core group defining a local group memory with a capacity 'CM' equal to the sum of the capacities 'Cm' of the local core memories of the cores belonging to the same group; and executing the neural operation by transmitting to the core groups operands complementary to the operands preloaded in the local group memory, and performing by the computing unit of said assigned computing cores the neural operation with the set of preloaded and complementary operands.

System and Method of Computation for the Inference of Convolutional Neural Networks The present invention relates to a method of computation for the inference of a convolutional neural network implemented on a multi-core computing platform, each core comprising a local core memory of capacity 'Cm' and a computing unit, the cores being grouped into groups of cores, such that in a group, one core is assigned to the computation of neural operations and is connected via neighbor links to at least one immediate neighboring core.The method includes, during inference, steps consisting of preloading a subset of operands required to perform a neural operation into the local core memories of the core groups. The local core memories of a core group define a local group memory with a capacity 'CM' equal to the sum of the capacities 'Cm' of the local core memories of the cores belonging to the same group. The neural operation is then executed by transmitting to the core groups operands complementary to the operands preloaded into the local group memory, and by performing the neural operation with the set of preloaded and complementary operands using the processing unit of said assigned processing cores. Figure 5 illustrates this in the abstract.

The present disclosure involves systems, software, and computer implemented methods for integrating data privacy integration protocols across system landscapes. One example method includes receiving, at a first tenant of a kernel service, a message from a first application in a first landscape. Data from the message is provided to a core component of the kernel service that communicates with multiple tenants of the kernel service. The core component stores data from the message in a core storage area accessible by multiple tenants of the kernel service. The first tenant performs, in the first landscape, a first processing of the message using data in the core storage area for which the first tenant is authorized. The core component initiates a second processing of the message by a second tenant of the kernel service in a second landscape using data in the core storage area for which the second tenant is authorized.

An integrated circuit package may include chiplets. Each chiplet may include at least one compute core, memory, microcontroller, and accelerator. Each chiplet may also include a network providing inter-chiplet and intra-chiplet connectivity. The network may have switches arranged in a hierarchical tree structure. The switches in an edge level may each be coupled to at least one address module. An address module may determine a physical address referring to a memory region of a shared memory for a job to be performed by the chiplet, generate a packet for the job, and determine a path through which the packet may be transferred. The address module may handle memory failures by remapping predetermined paths to alternative paths. The networks may facilitate connectivity between the package and one or more other packages. These packages may be stacked in a rack. The switch networks may facilitate connectivity between the rack with another rack.

The application discloses an internal and external network transmission system applied to the field of data transmission system, which comprises a core storage layer, an open storage layer and a communication terminal through an internal network end, the core storage layer is connected with the communication terminal through the open storage layer, and the communication terminal is connected with an external network end through an operator; the open storage layer comprises an open database, a temporary mirror database and a switching data processing unit; a plurality of permission data layers are arranged in the open database, and the temporary mirror database is matched with the temporary mirror database in the temporary mirror database; an intermediate data queue comprises an access permission filter, a real-time data queue and a non-real-time data queue. The permission filter of the external network access data is realized on the outside of the internal network end, so that the real-time data queue and the non-real-time queue are formed, the two queues are respectively interacted with different databases, the interaction results are interacted with the core database through a security mirror, and the security protection of the internal network data in the internal and external network data transmission process is effectively ensured.

The invention relates to the technical field of data processing, can be applied to business scenes such as financial data auditing and risk control and medical diagnosis, and provides a business data management method, system and device based on a multi-modal loop and a medium. Generating a to-be-evaluated feature vector and storing the to-be-evaluated feature vector into a temporary storage area of the feature pool; then, on the basis of historical high-value features stored in the core area, prediction labels and confidence coefficients are automatically generated for the features of the temporary storage area, and high-value samples are screened out according to the prediction labels and the confidence coefficients and used for iteratively updating a service model; and finally, transferring the high-value sample meeting the reflux condition from the temporary storage area to the core area for storage through value evaluation, so as to realize continuous precipitation and reuse of the characteristics. According to the embodiment of the invention, by constructing the multi-modal feature pool and designing a dynamic backflow mechanism between the temporary storage area and the core storage area, closed-loop flow of service data among cross-modal characterization, value evaluation and model iteration is effectively realized.

This application discloses a method and related equipment for calculating three-dimensional sparse Fourier transform, belonging to the field of data processing technology. The method includes: receiving a data packet transmitted by the main processor in response to a three-dimensional sparse Fourier transform calculation instruction; performing a three-dimensional sparse Fourier transform calculation process based on the data packet and in conjunction with the on-chip core storage of the coprocessor to obtain the three-dimensional sparse Fourier transform calculation result; and returning the three-dimensional sparse Fourier transform calculation result to the main processor. This application, by adopting a collaborative hardware architecture design of the main processor and coprocessor, clarifies the task boundaries of different processors and effectively reduces the frequent data transfer between computation and storage units by combining the on-chip core storage of the coprocessor to perform the three-dimensional sparse Fourier transform calculation. This significantly reduces data transmission overhead, greatly shortens the computation cycle of large-scale systems, and reduces computing power consumption.

The invention discloses a high-availability and elastic expansion system and method for a distributed database, relates to the technical field of distributed databases, and solves the problems that a large number of personal computing devices and commercial computing devices in an enterprise cannot be effectively utilized, and a special server storage device is directly full of storage, is stuck and cannot be used. A high availability and elastic expansion system and method for a distributed database, comprising a heterogeneous resource pool for storing various data in various databases, the heterogeneous resource pool comprising a storage node and a computing node, the computing node being used for analyzing and processing the input data, the storage node being used for storing the analyzed data; and the resource management module is used for registering, discovering and monitoring the state information of all nodes in the heterogeneous resource pool in real time. According to the method, the utilization rate of the core storage node is reduced in a mode of preferentially utilizing the edge storage node for storage, and elastic expansion of data storage is realized.

The application relates to the field of magnetic storage, in particular to a magnetic storage unit structure. The application replaces the [ferromagnetic / non-magnetic layer]n multilayer coupling structure or the ferromagnetic layer / antiferromagnetic layer structure commonly used in the current SOT-MRAM core storage unit with the exchange bias interlayer structure ferromagnetic layer / ultra-thin metal interlayer / antiferromagnetic layer structure. Through the addition of the ultra-thin metal interlayer, the ferromagnetic and antiferromagnetic interface magnetic moments can be controlled by changing the interlayer metal material and its thickness, so that the coexistence of in-plane and out-of-plane exchange bias in the exchange bias structure is realized. Meanwhile, for storage, the out-of-plane exchange bias field is used to ensure the stability of the fixed layer of the storage unit, and the in-plane exchange bias field is used as the replacement of the required in-plane lateral field, so that the low-power consumption flipping of the information storage layer is realized without increasing the lateral magnetic field providing circuit, and the purpose of reducing the overall structure complexity is achieved.

The application belongs to the technical field of core supply and relates to a cable core supply equipment. The core storage device is provided with a monitoring device for monitoring whether the core storage device is internally provided with cores. The limiting device limits the movement of the core storage device through the monitoring device. The storage pushing device is provided with a core pushing-out device. When a wire spool is installed in the core storage device, the cores are pushed through the monitoring device, the storage pushing device stores a plurality of core storage devices, and then the cores in the core storage device are discharged through the monitoring device. The core pushing-out device pushes the cores passing through the monitoring device forward. When the cores in the core storage device are discharged, the limiting device cannot limit the monitoring device without cores because there is no extrusion of the monitoring device by the cores. The storage pushing device pushes the core storage device to move and ejects the core storage device without cores from the core storage device with cores.

1. Name of the product in this design: Core Storage Box (2). 2. Purpose of this design: For storing rock cores. 3. The key design feature of this product is its shape. 4. The image or photograph that best illustrates the design's key points: 3D rendering 1.

1. Name of the product in this design: Core Storage Box (1). 2. Purpose of this design: For storing rock cores. 3. The key design feature of this product is its shape. 4. The image or photograph that best illustrates the design's key points: a 3D model.