67 results about "Core Storage" patented technology

The invention discloses a cross-modal travel knowledge graph construction system based on a large language model. The cross-modal travel knowledge graph construction system comprises a data source module, a data access module, a change identification module, an incremental updating module, a verification feedback module, a core storage and application module and a technical base module. According to the method, optimization is carried out around dynamic updating accuracy, real-time efficiency and scene adaptability, and four dimensions of hidden conflict resolution, real-time processing efficiency, small and medium main body access and multi-modal deep fusion are improved.

The invention belongs to the technical field of engineering cost, and discloses an engineering cost data security management system based on a block chain. The system is composed of an Internet of Things data acquisition and preprocessing module, a heterogeneous block chain core storage module, a dynamic consensus verification module, an intelligent contract and AI decision module, a multi-dimensional audit tracking module, a cross-chain authority management module and an intelligent early warning and decision support module. Data hierarchical storage is realized through a main chain-subchain-side chain three-level block chain architecture, key data is encrypted, a dynamic permission matrix of a cross-chain permission management module is matched, a whole-process security barrier from collection to interaction is constructed, data collected by an Internet of Things terminal is preprocessed to generate a non-tampering verification certificate, and the verification certificate is stored in a database. A dynamic consensus mechanism ensures compliance of uplink data, a multi-dimensional auditing module tracks an operation track in real time, data tampering and unauthorized access risks are eradicated from the technical level, and meanwhile the requirement of a data security law for sensitive information protection is met.

The invention relates to the technical field of storage and calculation integration, in particular to a multi-core storage and calculation integration-oriented routing system and electronic equipment, the system comprises a plurality of storage and calculation integration cores, each storage and calculation integration core comprises a plurality of storage and calculation macro units, a plurality of direction output interfaces, an analysis network-on-chip and a router, and the storage and calculation macro units are bound with the direction output interfaces; the analysis network-on-chip analyzes the header information of the data packet to determine the target transmission direction of the data packet, and when the target transmission direction is the same as the position direction of the target core, the direction output interface outputs data to the target core; and the router is used for generating a target planning path according to the target transmission direction and the position direction of the target core when the target transmission direction is different from the position direction of the target core, and transmitting the data packet to the target core according to the target planning path. Therefore, the problems of congestion of high-parallel signal winding between the memory macro-cell and the route, blockage caused by improper matching of data transmission directions, low path planning efficiency and the like in the prior art are solved.

The invention relates to a storage wafer structure and a forming method of a three-dimensional integrated device. A test chip is formed in a cutting area of the storage wafer structure, the test chip comprises a core storage module, an input and output module, a control module and a data channel module, and the performance and the yield of a storage unit in a chip area can be indirectly detected before the storage wafer structure is bonded with a logic circuit wafer by utilizing the test chip; the qualified storage wafer structure can be conveniently screened to be bonded with the logic circuit wafer, the yield of the three-dimensional integrated device comprising the storage wafer structure and the logic circuit wafer can be improved, and the scrap cost can be reduced. In the forming method of the three-dimensional integrated device, before the storage wafer structure and the logic circuit wafer are bonded, the test chip is used for testing, so that the yield is improved, and the scrap cost is reduced.

The invention discloses a DSP application deployment optimization method and system, a medium and a product, and the method comprises the steps: analyzing a to-be-deployed DSP application, extracting a directed acyclic graph, if operators in the directed acyclic graph are all in a support operator list of a target DSP chip, traversing the operators in the directed acyclic graph, and if the operators in the directed acyclic graph are all in the support operator list of the target DSP chip, determining that the operators in the directed acyclic graph are all in the support operator list of the target DSP chip; dividing the operators into intra-core storage operators and DDR (Double Data Rate) storage operators according to storage requirements of the operators and intra-core storage capacity of a target DSP (Digital Signal Processor) chip, and distributing and calculating the number of cores; storing configuration information of all operators in an end side model file; and deploying the end side model file of the to-be-deployed DSP application to the target DSP chip by using the deployment tool. The invention aims at solving the problem of low efficiency of the current DSP application deployment method by adaptively configuring the storage type and the calculation core number in the application deployment process, and realizing efficient and universal DSP application deployment optimization.

The invention provides a thermal shock buffering device and an opening control method thereof, the thermal shock buffering device comprises two buffering devices, each buffering device comprises a hollow shell, a storage chip is clamped between the two shells, and the shells are formed through a blow molding process. The shell is made of other molding materials not limited to PP, PE, HDPE or PET, the cost of raw materials is reduced, and meanwhile the phenomenon that the whole device loses efficacy due to the fact that a pressure relief hole of the shell is blocked and other sealing performance problems exist is avoided. The shell is integrally formed through the blow molding process, the production process is simple, and the sealing performance of the shell is improved. The shell is integrally formed, the structure is simplified, the internal space of the phase change unit is increased, the volume of the phase change material is increased, and thermal performance is improved. After the phase change units of the two shells are assembled, a protection cavity is formed in the center, and the interior of the protection cavity is used for installing and protecting a core storage chip.

The present application relates to the technical field of core transfer, in particular to a core storage and transfer box with geological information recording, which solves the problems of the core storage and transfer box, such as the single core adaptation of groove position fixation, the complexity of taking and placing, the damage of core due to transportation movement and collision, the simple concave-convex positioning without locking of stacking, the easy falling of transfer, the easy falling of information sticker outside, the low efficiency and error of checking, etc. The box body structure is internally provided with a lifting adjusting mechanism. The core sample is placed between two groups of limiting plates, the position of the limiting plate is locked by a locking screw, the lateral clamping and fixation of the core is realized, the flexible limiting and clamping of the two ends of the core sample are realized by a blocking plate, the storage of cores with different diameters and different length specifications can be adapted, the versatility is high, the core shaking, collision and damage due to knocking during the transfer process are effectively avoided, and the integrity of the geological core sample is fully protected.

First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.

A storage device reduces power consumption and processes a first command in a low power mode. The storage device includes a controller to process host commands when the storage device is in a fully active state and to enter a deactivated state when the storage device enters the low power mode. An always-on processor on the storage device enters a sleep state when the storage device enters the low power mode. The always-on processor receives a notification of an incoming host command when the storage device is in the low power mode. When the always-on processor determines that the incoming command is a first command, the always-on processor processes the first command and remains in the sleep state. When the always-on processor determines the incoming command is a second command, the always-on processor may activate the controller to return the storage device to the fully active state.

The utility model belongs to the field of transformer part production, and discloses a single-frame iron core storage device which comprises a tray and a supporting piece fixedly arranged on the tray, three supporting faces evenly distributed in the circumferential direction of the tray are arranged on the supporting piece, and the included angle between any two adjacent supporting faces on a horizontal projection plane is 60 degrees. A limiting check block is fixedly arranged at the position, corresponding to the radial outer side of each supporting face, of the surface of the tray, and a clamping space used for containing the single-frame iron core is formed between each limiting check block and the corresponding supporting face; on the horizontal projection plane, the top edge of the supporting face is arranged close to the center of the tray, and the bottom edge of the supporting face is arranged close to the edge of the tray. According to the utility model, three single-frame iron cores with the same energy efficiency grade can be stably stored at one place; the centralized storage device is suitable for the transformer part production industry and used for centralized storage of the three single-frame iron cores before splicing.

The invention discloses an intelligent logistics warehousing system management method and system based on big data, and relates to the technical field of warehousing system management methods, and the method comprises the steps: determining a data storage system between warehousing data storage spaces according to the data load of each warehousing data storage space and a current input data packet; determining a to-be-completed storage event of the intelligent logistics storage system based on big data analysis of the current input data packet; and determining the core storage data according to the storage event to be completed, the storage data of the plurality of original storage nodes and the storage data of the newly added storage nodes, thereby improving the accuracy of the core storage data. Therefore, the multiple intelligent logistics storage plans are determined based on the storage work list, the data management system of each intelligent logistics storage plan is determined according to each intelligent logistics storage plan, the corresponding newly-added storage node and the current working state of the intelligent logistics storage system, and data management of each intelligent logistics storage plan is optimized.

The present application relates to the technical field of data processing, and especially relates to a sparse direct solution method based on data kernel external storage, which comprises the following steps: obtaining a coefficient matrix of a high-dimension sparse linear equation group, analyzing a non-zero element distribution mode and a matrix topological structure to establish a task dependency relationship; detecting a system memory capacity and a disk performance parameter to set a slice size parameter, dividing a wavefront matrix into data slices with balanced floating-point operation amounts to execute a left-looking numerical decomposition; creating a message queue and a monitoring mechanism to realize asynchronous disk storage; reading data from the disk to execute a numerical update cycle; and establishing a back substitution solution memory work area to generate a numerical solution by using a previous generation back substitution algorithm. The present application utilizes disk storage to relieve memory pressure and supports large-scale finite element simulation application.

An apparatus includes a first switch coupled between a first voltage source and input / output (I / O) circuitry of a memory device, wherein the first voltage source is to supply power to core memory circuitry of the memory device. A second switch is coupled between a second voltage source and the I / O circuitry. Control logic is coupled with the first and second switches and to cause the second switch to be activated to permit current to flow from the second voltage source to the I / O circuitry. The control logic, in response to detecting a current draw from the I / O circuitry that satisfies a first threshold criterion, causes the first switch to be activated.

Apparatuses and methods for an integrated device with trusted execution environment (TEE) confidential computing support are disclosed. An apparatus and method for extending IO device security protocols to an integrated processor. For example, an example processor package includes: a plurality of cores to execute instructions; an interconnect structure coupled to the plurality of cores; a memory interface circuit coupled to the interconnect structure, the memory interface circuit to couple the plurality of cores to one or more memories; a root complex comprising: a security circuit operable as a root of trust (RoT) and a bridge to the interconnect structure, the security circuit for establishing secure communications with one or more root complex integrated endpoint (RCiEP) devices integrated into the processor package; and a security protocol and data model (SPDM) engine of the security circuit for providing RCiEP encryption and SPDM protocol services to establish a secure communication channel with each RCiEP device.

The invention discloses a design method of an AI compiler of a multi-core end side AI chip, and belongs to the field of AI chip scheduling systems. According to the method, a multi-core storage allocation strategy, a synchronization mechanism and code generation optimization Pass are set in the compiling process, and efficient scheduling and modular management of the multi-core parallel computing tasks are achieved. The method is based on a multi-stage intermediate representation framework popular in the industry, corresponding functions are easy to develop, a multi-core storage distribution and synchronization mechanism can be defined in a specific Pass, modular management is achieved, the stability and expansibility of a compiler can be improved while the flexibility of a multi-core framework is guaranteed, and the method is suitable for popularization and application. Therefore, the performance and the development efficiency of the end-side AI chip in a complex application scene are improved.

The present invention relates to a memory wafer structure and a method for forming a three-dimensional integrated device. A test chip is formed in the cutting area of ​​the memory wafer structure. The test chip includes a core memory module, an input / output module, a control module, and a data channel module. The test chip can be used to indirectly test the performance and yield of the memory cells in the chip area before the memory wafer structure is bonded to a logic circuit wafer. This facilitates screening of qualified memory wafer structures for bonding to the logic circuit wafer, helps improve the yield of the three-dimensional integrated device including the memory wafer structure and the logic circuit wafer, and reduces scrap costs. In the method for forming the three-dimensional integrated device, the test chip is used to perform testing before bonding the memory wafer structure to the logic circuit wafer, which helps improve the yield and reduce scrap costs.

The application provides an electronic archive storage method and system, which comprises the following steps: creating a corresponding core storage pool in real time according to a plurality of groups of heterogeneous server clusters, and receiving an original electronic archive input by a user in real time; splitting the original electronic archive into a plurality of data segments according to the content correlation in the original electronic archive, and generating an independent encryption key adapted to each data segment in real time to generate a corresponding encrypted data segment; storing each encrypted data segment in the internal part of the plurality of groups of heterogeneous server clusters, and setting a corresponding filtering gateway at the access entrance of the core storage pool; and performing real-time filtering processing on the access request received in real time through the filtering gateway to complete the storage of the original electronic archive correspondingly. The application can greatly improve the confidentiality of the electronic archive and improve the storage efficiency of the electronic archive.

Provided are a distributed parallel computing based graph computing method, a distributed parallel computing system and a computer readable medium. A graph computing method comprises: obtaining data of a graph to be computed, the graph comprising a plurality of vertices and edges; storing the graph according to a compressed sparse row format, and storing the graph in a sparse matrix form, wherein all adjacent edges having a same vertex are continuously stored, and an offset array is used to support an index function thereof; and for subgraphs in which the degrees of both source vertices and target vertices are greater than a predetermined threshold, in forward graphs, performing segmentation according to target vertices, i.e., the column of a matrix, and in reverse graphs, performing segmentation according to source vertices, i.e., the row of the matrix, and further dividing the subgraph into a plurality of segmented subgraph (SSG) components, so that a target vertex in each SSG is limited within a preset range. According to the SSG method of the embodiment for a high-degree vertex, the conventional problem that the space-time locality of accessing data of an adjacent vertex is poor due to a large vertex range of a single large graph is avoided or relieved.

A storage device reduces power consumption and processes a first command in a low power mode. The storage device includes a controller to process host commands when the storage device is in a fully active state and to enter a deactivated state when the storage device enters the low power mode. An always-on processor on the storage device enters a sleep state when the storage device enters the low power mode. The always-on processor receives a notification of an incoming host command when the storage device is in the low power mode. When the always-on processor determines that the incoming command is a first command, the always-on processor processes the first command and remains in the sleep state. When the always-on processor determines the incoming command is a second command, the always-on processor may activate the controller to return the storage device to the fully active state.

The present invention belongs to the field of rock storage technology, and specifically relates to a display type rock core storage, comprising a box body, a box cover hinged on the box body, and a locking assembly arranged on the rear side of the box body, the front side of the box body has an opening, the box cover can be flipped relative to the box body to open and close the opening, when the box cover is flipped to the rear side of the box body to open the opening, the locking assembly can fix the box cover to the rear side of the box body, in this state, the box cover can contact the ground to support the box body in an inclined state from front to back and downward to upward, and the storage can store rock cores. In addition, when the rock cores need to be displayed, the box body can be supported in an inclined state to allow the rock cores to be in an inclined state, that is, the side and upper end faces of the rock cores are both tilted toward the upper side, so that the observer can observe both the side and end faces of the rock cores when standing and observing, so there is no need for the observer to lean over or even squat to observe, so the storage is conducive to displaying rock cores.

The application relates to the technical field of engineering geology exploration, and discloses a 3D scanning core characteristic parameter identification system and method, which comprises a core storage module and a 3D scanning module; the method comprises the following steps: separating complete and fragmented cores by self-adaptive cleaning and separation of drilling core samples, forming a space-attribute binding initial data set; dynamically adjusting the height and levelness of a 3D laser scanner by an automatic numerical control platform, generating an optimal scanning path topology network covering all core boxes; the scanning path topology network feeds back point cloud coverage in real time, dynamically adjusts the rotation angle, and outputs a full-angle high-density core point cloud sequence; the full-angle high-density core point cloud sequence is fused by multi-scale features, and an automatic columnar chart, a quantitative parameter set and a joint parameter package are generated. Through automatic and high-precision scanning and data analysis, the application realizes digitalized collection of cores and accurate calculation of geological parameters, and improves the efficiency and quality of geological exploration.

The invention discloses a neural network load mapping method and device for a multi-core storage and calculation integrated chip, and belongs to the field of artificial intelligence hardware acceleration and in-storage calculation. According to the method, a neural network load directed calculation graph is obtained by extracting matrix multiplication operators of a neural network and a data dependency relationship between the operators, and then a storage and calculation integrated chip load mapping result is generated according to the neural network load directed calculation graph and architecture parameters of the storage and calculation integrated chip. And a chip configuration program is generated in combination with configuration register information in chip architecture parameters, so that automatic and efficient mapping of the neural network is realized.

The application discloses a neural network load mapping method and device of a multi-core storage and computing integrated chip, and belongs to the field of artificial intelligence hardware acceleration and in-memory computing. The method extracts a matrix multiplication operator of a neural network and a data dependency relationship between the operators, obtains a neural network load directed computation graph, and then generates a storage and computing integrated chip load mapping result according to the neural network load directed computation graph and architecture parameters of the storage and computing integrated chip, and further generates a chip configuration program in combination with configuration register information in the chip architecture parameters, so as to realize automatic and efficient mapping of the neural network.

The embodiment of the invention provides a lake and warehouse integrated data processing system, and relates to the field of big data processing. A data access layer accesses data from a plurality of heterogeneous data sources; the object storage unit is used for persistently storing the initial data accessed from the data access layer in an original data format to form an original data area; the core storage engine unit adopts a large-scale parallel processing architecture and manages a refined data area through an incremental data snapshot mechanism; the unified metadata service manages metadata in a unified manner, and records a derivative relationship and structure mapping; the data processing layer extracts data from the original data area, performs conversion and loading operation, writes the processed data into the refined data area, and is integrated with a data quality verification module; and the data service layer provides a uniform data access interface and can query and analyze data in the original data area and the refined data area. The problems of data islands, performance bottlenecks, treatment difficulty and the like in the prior art are effectively solved.

The invention discloses a secure mobile storage device and method integrating multiple self-destruction and protection mechanisms, and belongs to the field of mobile storage security. Aiming at the problem of insufficient safety protection of the existing mobile storage equipment, a five-layer composite protection framework is adopted. A shell layer is integrated with micron-sized pressure and temperature sensors to monitor physical tampering; the protection circuit layer realizes millisecond-level circuit break protection by using a multi-state silicon controlled rectifier array; the dynamic encryption module is used for dynamically refreshing a secret key based on an FPGA and a chaotic mapping algorithm; the core storage layer adopts a 3D XPoint medium to support rapid overwriting; and the self-destruction execution unit is used for physically destroying the data by utilizing the nanoscale corrosive gas micro-capsule. And defining a threat scoring model, dynamically adjusting a threshold value, and implementing a multi-stage self-destruction mechanism. An improved Logistic-Tent double-chaos system is combined with real-time entropy source modulation of an acceleration sensor to generate a secret key, so that the safety and the randomness are enhanced. The security and reliability of the mobile storage device are improved, and the data security is effectively guaranteed.

The purpose of this project is to provide a core model generation method that uses three-dimensional model data of the front and back of a core storage box containing a columnar core, efficiently joins and shapes the data, removes unnecessary parts, and then constructs a cylindrical three-dimensional model along the depth direction. [Solution] A method for generating a core model using three-dimensional models of the front and back surfaces obtained for a storage box containing a columnar core, comprising: a first step of removing parts other than the columnar core from the three-dimensional models of the front and back surfaces based on a specified area; a second step of aligning and joining the three-dimensional models of the front and back surfaces from which parts other than the columnar core have been removed in the first step based on a reference plane; and a third step of joining the three-dimensional models of multiple columnar cores aligned and joined in the second step along the depth direction.

The utility model discloses a square silicon core stack frame relates to silicon core storage equipment technical field, including base, base bottom four corners all are rotatoryly connected with universal wheel, the base top is provided with a plurality of support frame, support frame outside is provided with elevating system, the base top is provided with auxiliary cooling mechanism. The utility model discloses a square silicon core stack frame, elevating system passes through the rotation handle and drives the rotation of worm, the rotation of screw rod is driven by worm wheel engagement, and fixed block and support frame are driven by screw sleeve and lift, and the synchronous adjustment of the height of each layer support frame is realized through the telescopic cooperation of articulated frame, adapts the storage demand of different size square silicon core, and convenient to take and put operation, improves the use convenience.

The present invention provides a financial data encryption transmission system and method based on a layered security architecture. The system comprises an outer protective layer, a data transmission layer, a financial data processing layer, and a core storage layer, which are arranged in sequence from the outside to the inside. The outer protective layer adopts a physical tamper-proof shell made of an alloy material and a hexagonal honeycomb electromagnetic shielding grid to achieve a shielding effectiveness of not less than 60dB. The data transmission layer adopts high-speed differential signal transmission to ensure that the differential signal integrity is greater than 0.85. The financial data processing layer implements a dual encryption mechanism and combines the SHA-3 / SM3 algorithm for data verification. The core storage layer adopts a (t, k) threshold scheme for key sharding storage. Through multiple physical protections, high-reliability data transmission, and distributed key storage, the present invention effectively solves the problems of insufficient physical security protection and poor transmission reliability in the prior art, thereby improving the security of financial data transmission.

The present invention provides a storage device, a computer system, and a data transfer program. An edge storage device (100) is connected to other storage devices capable of performing deduplication and management on file data in units of predetermined data blocks via a network, and includes a CPU (111). When the CPU (111) transfers data of a newly created file or an updated file to other storage devices, it determines whether to send the differential part or the fingerprint of the differential data block, which is the data block containing the differential part, to the core storage device based on the size of the differential part and the size of the fingerprint of the differential data block, and sends the differential part or the fingerprint to the core storage device based on the determination result. According to the present invention, the communication volume between storage devices for transferring data can be reduced.