Storage wafer structure and method for forming three-dimensional integrated device

Abstract

The present invention relates to a memory wafer structure and a method for forming a three-dimensional integrated device. A test chip is formed in the cutting area of ​​the memory wafer structure. The test chip includes a core memory module, an input / output module, a control module, and a data channel module. The test chip can be used to indirectly test the performance and yield of the memory cells in the chip area before the memory wafer structure is bonded to a logic circuit wafer. This facilitates screening of qualified memory wafer structures for bonding to the logic circuit wafer, helps improve the yield of the three-dimensional integrated device including the memory wafer structure and the logic circuit wafer, and reduces scrap costs. In the method for forming the three-dimensional integrated device, the test chip is used to perform testing before bonding the memory wafer structure to the logic circuit wafer, which helps improve the yield and reduce scrap costs.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a storage wafer structure and a method for forming a three-dimensional integrated device. Background Art

[0002] Three-dimensional integration technology can achieve high-performance integrated interconnect circuits and is a new technology for obtaining high-performance chips. Taking the manufacturing process of a three-dimensional integrated memory chip as an example, the memory device wafer and the logic circuit wafer are first manufactured separately, and then the two are vertically bonded to form a stacked structure, in which the circuits of the two wafer chip areas are interconnected. The three-dimensional integrated memory chip obtained by dividing the stacked structure is then vertically connected to the logic circuit layer and the storage layer. In addition, as the market demand for memory continues to grow, the existing process will vertically bond two or more memory device wafers to form multi-layer storage before bonding the logic circuit wafer to increase storage capacity and storage density.

[0003] The yield of three-dimensional integrated chips is related to the yield of the memory device wafer and the logic circuit wafer. However, the current testing of memory device wafers is relatively simple, usually only involving electrical performance testing at the single device level (such as WAT (wafer acceptance test)). For the read and write performance testing of three-dimensional integrated chips, it is necessary to input a control signal from the logic circuit wafer to the memory device wafer through the signal transmission channel between the two after the memory device wafer and the logic circuit wafer are bonded. If the memory device wafer is tested to be defective, the qualified logic circuit wafer bonded to it will also be scrapped. In addition, the production cost of logic circuit wafers is usually high, resulting in high scrapping costs. Summary of the Invention

[0004] In order to test the read and write performance of a memory device wafer or a stacked structure of memory device wafers before bonding with a logic circuit wafer, improve the yield of a three-dimensional integrated device including a memory wafer structure and a logic wafer structure, avoid the waste of logic circuit wafers that occurs when the read and write performance is tested only after bonding, and reduce scrap costs, the present invention provides a memory wafer structure and a method for forming a three-dimensional integrated device.

[0005] In one aspect, the present invention provides a memory wafer structure comprising a plurality of chip regions and a dicing region located around each of the chip regions, wherein each chip region comprises a memory chip, each memory chip comprises a plurality of memory cells comprising a memory device array, and wherein the dicing region comprises a test chip, wherein the test chip comprises:

[0006] a core memory module comprising a memory device array, wherein the memory device array in the core memory module is replicated in at least a portion of the memory device array in one of the memory cells;

[0007] An input / output module, configured to connect external signals to the test chip and output signals detected by the test chip;

[0008] a control module, configured to generate a control signal according to input information of the input / output module; and

[0009] The data channel module is used to form a bidirectional data transmission channel between the input and output module and the core storage module according to the control signal of the control module.

[0010] Optionally, the amount of data that can be stored in the memory device array of the core memory module is less than or equal to the amount of data that can be stored in the memory device array of one of the memory units.

[0011] Optionally, the core memory module and the memory unit further include local sense amplifiers corresponding to the respective internal memory device arrays; the control module includes a write controller, a read controller, a row decoder, and a column decoder.

[0012] Optionally, the test chip further includes an analog voltage module, which includes a low voltage dropout linear regulator and / or a charge pump replicated in the storage unit, and is used to provide the core storage module with the voltage required for the operation of the corresponding storage device array.

[0013] Optionally, the test chip also includes an electric fuse module, which is copied from the electric fuse module inside the storage unit. In the test chip, the electric fuse module is used to obtain the programming voltage input by the input and output module, and program the electric fuse according to the control signal of the control module, and send the formed voltage monitoring signal to the analog voltage module.

[0014] Optionally, the input-output module includes a plurality of solder pads and a solder pad ring connected to the plurality of solder pads, and the plurality of solder pads connect the external signal to the test chip, wherein the external signal is used to test at least one of the core storage module, the analog voltage module and the electric fuse module, and the plurality of solder pads output test results to determine whether the storage unit in the chip area is qualified.

[0015] Optionally, the input-output module includes a plurality of solder pads and a solder pad ring connected to the plurality of solder pads, and the plurality of solder pads connect the external signal to the test chip; wherein the external signal includes test instructions and test data for testing the test chip, and by writing the test data into the core storage module and then reading it out, the plurality of solder pads output the test results to determine whether the storage unit in the chip area is qualified.

[0016] Optionally, the control module and the data channel module both receive a group of signals including an asynchronous interrupt signal, a clock signal and a power-on reset signal from the input-output module; the data channel module also receives input data signals from the input-output module, control signals from the control module and feedback data signals from the core storage module.

[0017] Optionally, the data channel module performs serial-to-parallel conversion on the serial data transmitted by the input data signal to form a parallel input data signal output to the core storage module, and also performs parallel-to-serial conversion on the parallel data transmitted by the feedback data signal to form a serial output signal output to the input-output module.

[0018] Optionally, the memory wafer structure includes one memory device wafer or two or more memory device wafers that are vertically stacked and bonded.

[0019] Optionally, when the storage wafer structure includes two or more storage device wafers vertically stacked and connected, the cutting area of ​​each storage device wafer is formed with the test chip, and the input and output modules in the multiple test chips respectively located in each layer of the storage device wafer and stacked vertically are vertically connected.

[0020] In another aspect, the present invention provides a method for forming a three-dimensional integrated device, the method comprising:

[0021] Obtaining at least one of the aforementioned memory wafer structures;

[0022] By testing the test chip on the storage wafer structure, the yield of the storage unit in the chip area of ​​the storage wafer structure is estimated, and the storage wafer structure that has passed the test is screened out; and

[0023] The memory wafer structure that has passed the test is bonded and interconnected with a logic circuit wafer.

[0024] In the storage wafer structure provided by the present invention, a test chip is formed in the cutting area, and the test chip includes a core storage module, an input and output module, a control module and a data channel module. By testing the test chip, it is possible to indirectly obtain information on whether the storage unit in the chip area is qualified before the storage wafer structure is bonded to the logic circuit wafer, thereby facilitating the screening of the qualified or yield-satisfying storage wafer structure and the logic circuit wafer for bonding, which helps to improve the yield of the three-dimensional integrated device including the storage wafer structure and the logic circuit wafer and reduce the scrap cost.

[0025] In the method for forming a three-dimensional integrated device provided by the present invention, after obtaining the above-mentioned storage wafer structure for three-dimensional integration, the yield of the storage unit in the chip area of ​​the storage wafer structure is inferred by testing the test chip on the storage wafer structure, and the storage wafer structure that has passed the test is screened out and bonded and interconnected with the logic circuit wafer, which helps to improve the yield of the three-dimensional integrated device including the storage wafer structure and the logic circuit wafer and reduce the scrap cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 FIG. 1 is a partial plan view of a memory wafer structure according to an embodiment of the present invention.

[0027] Figure 2 Schematic diagram of the structure of a test chip in one embodiment of the present invention.

[0028] Figure 3 Schematic diagram of the pad arrangement of the input and output modules in the memory wafer structure according to an embodiment of the present invention.

[0029] Figure 4 It is a schematic flow chart of a method for forming a three-dimensional integrated device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The following is a further detailed description of the memory wafer structure and method for forming a three-dimensional integrated device of the present invention, in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are all in a very simplified form and are not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0031] For memory device wafers formed using wafer-level semiconductor processes, multiple memory devices (such as DRAM, SRAM, or other memory devices) are usually arranged into an array, wherein the gates of the memory devices are connected to form multiple word lines, and the drains of the devices are connected to form multiple bit lines. In addition, the multiple memory device arrays can share a set of word lines and a set of bit lines. Therefore, when the memory chip is operating, the structure including the multiple memory device arrays can be regarded as a memory unit, and the read and write operations of each memory unit can be independently controlled. However, when currently using wafer-level semiconductor processes to manufacture memory device wafers, the test structures formed in the scribe line (also known as the scribe line) of the wafer are relatively simple, typically including resistors, capacitors, diodes, MOS transistors, or independently controlled memory devices, etc., with the purpose of detecting the leakage current, threshold voltage (Vth), and turn-on current of the resistors, capacitors, and semiconductor devices. It can be seen that it only involves electrical performance testing at the level of a single device, with the purpose of detecting whether the process quality and the characteristics of the semiconductor device meet the requirements. These test structures cannot detect the circuit connection performance and read / write performance of the memory cell. However, as described in the background art, if the performance of the memory cell is tested only after the memory device wafer and the logic circuit wafer are bonded, the scrap cost is very high.

[0032] An embodiment of the present invention first relates to a storage wafer structure. Compared with existing storage device wafers, a test chip is formed in the cutting area. The test chip can be used to detect the connection performance and read-write performance of the circuit copied to the storage unit, so as to indirectly detect the performance and yield of the storage unit formed in the chip area. It can be used to screen the storage wafer structure to be bonded with the logic circuit wafer, which helps to improve the quality of the bonding structure and reduce scrap costs.

[0033] Figure 1 FIG. 1 is a partial plan view of a memory wafer structure according to an embodiment of the present invention. Figure 1 In the embodiment of the present invention, the memory wafer structure 100 includes a plurality of chip areas 10 and a dicing area 20 located around each chip area 10 , wherein the dicing area 20 is formed with a test chip TK.

[0034] Each chip region 10 is the area within the memory wafer structure 100 where a die is formed. Each chip region 10 includes a memory chip. The chip region 10 may include multiple memory cells that can be independently controlled to read and write data. Each memory cell includes multiple memory devices (such as DRAM or SRAM) and circuitry connected to the memory devices as required by the chip's operation. Each memory chip, for example, includes multiple memory cells comprising a memory device array. Each memory cell is, for example, a "bank," and each "bank" includes a group of memory device arrays that share wordline and bitline addresses. For example, a "bank" includes a memory device array with 16K wordlines and 16K bitlines, capable of storing 128M bits (i.e., 32M bytes) of data. Alternatively, a "bank" includes a memory device array with 2K wordlines and 16K bitlines, capable of storing 32M bits (i.e., 4M bytes) of data. In the following embodiments, the memory devices within the memory wafer structure 100 are, for example, DRAMs.

[0035] The dicing area 20 is the area where the memory wafer structure 100 is subsequently cut to obtain individual chips. In this embodiment, the dicing area 20 is formed with a test chip TK for indirectly testing the performance of the memory cells in the chip area 10. For example, circuit connectivity performance, such as whether internal word lines and / or bit lines are short-circuited or open-circuited, can be tested, and read and write performance can also be tested through read and write tests. Depending on testing needs and the area allowed by the dicing area 20, the dicing area 20 may also be formed with test marks and / or test structures for WAT testing. These test structures may include resistors, capacitors, diodes, MOS transistors, and independently controlled DRAM devices, and can test the leakage current, threshold voltage (Vth), and turn-on current of resistors, capacitors, and devices.

[0036] The memory wafer structure 100 of the embodiment of the present invention can be a single-layer memory device wafer, or two or more memory device wafers bonded vertically. Each memory device wafer can be formed using a wafer-level semiconductor process, wherein, while forming a plurality of the memory cells in the chip area 10, the test chip TK is also formed in the cutting area 20 to indirectly test the performance of the memory cells. Figure 1 , more than one test chip TK can be arranged in the cutting area 20, and one or more test chips TK can be tested as needed. Figure 2 and Figure 3 , the test chip TK according to the embodiment of the present invention is further described.

[0037] like Figure 2As shown, the test chip TK includes a core memory module 110 , which includes a memory device array that replicates at least a portion of a memory device array in one of the memory cells.

[0038] The size of the memory device array in core memory module 110 can be specifically set based on testing requirements and the area of ​​the dicing region. Depending on the size of the internal memory device array, the amount of data that can be stored in core memory module 110 varies. In this embodiment, the amount of data that can be stored in the memory device array of core memory module 110 is less than or equal to the amount of data that can be stored in the memory device array of one of the memory cells. For example, in one embodiment, the amount of data that can be stored in the memory device array of the core memory module 110 is equal to the amount of data that can be stored in the memory device array of one of the memory cells. For example, the amount of data that can be stored in the core memory module 110 and the amount of data that can be stored in one of the memory cells (or one bank) are both 32 Mbytes. The memory device array in the core memory module 110 is the same size as the memory device array in one of the memory cells, both including 16K word lines and 16K bit lines. In another embodiment, due to the area limitation of the cutting area 20, the amount of data that can be stored in the memory device array of the core memory module 110 is equal to half the amount of data that can be stored in the memory device array of one of the memory cells (or one bank). For example, the amount of data that can be stored in the memory device array of one of the memory cells is 32 Mbytes, while the amount of data that can be stored in the memory device array of the core memory module 110 is 16 Mbyte. In this case, the memory device array in the core memory module 110 includes, for example, 8K word lines and 16K bit lines, or 16K word lines and 8K bit lines.

[0039] In some embodiments, the core memory module 110 further includes structures other than the memory device array. For example, the core memory module 110 and the memory unit further include local sense amplifiers corresponding to the respective internal memory device arrays.

[0040] like Figure 2 and Figure 3 As shown, the test chip TK includes an input / output module 120, which is used to connect external signals to the test chip TK and output signals detected by the test chip TK. Furthermore, the input / output module 120 may include multiple pads and a pad ring 122 connected to the pads. When testing the test chip TK, external signals are connected to the test chip TK via the pads.

[0041] In one embodiment, the external signal includes a test instruction and test data for testing the test chip TK (for example, via Figure 2The pads PAD_SI shown in FIG. 1 , which follow the pads PAD_SCLK, transmit the cmd command and address in a clocked manner. By writing the test data into the core memory module 110 and then reading it out, the multiple pads output the test results to determine whether the memory cells in the chip region 10 are qualified. The present invention is not limited to this. For example, in another embodiment, the external signal is used to test at least one of the core memory module 110, the analog voltage module 150, and the electrical fuse module 160. The multiple pads output the test results to determine whether the memory cells in the chip region 10 are qualified.

[0042] like Figure 2 As shown, the test chip TK further includes a control module 130 and a data channel module 140. The control module 130 is configured to generate control signals based on signals input from the input / output module 120. The data channel module 140 is configured to establish a bidirectional data transmission channel between the input / output module 120 and the core storage module 110 based on the control signals from the control module 130.

[0043] As an example, the control module 130 may include a write controller, a read controller, a row decoder, and a column decoder corresponding to the memory device array within the core memory module 110 .

[0044] like Figure 2 As shown, in some embodiments, the test chip TK may further include an analog voltage module 150, which includes a low-dropout linear regulator and / or a charge pump replicated in the memory cells of the chip area 10. The analog voltage module 150 is used to provide the core memory module 110 with the voltage required for the operation of the corresponding memory device array (for example, as shown in FIG. Figure 2 The analog voltage module 150 may also send a basic clock frequency signal OSC1MS and a voltage monitoring signal VMONI to the pad ring 122.

[0045] The test chip TK may further include an electric fuse module 160, which is a copy of the electric fuse module formed in the memory cell of the chip area 10. In the test chip TK, the electric fuse module 160 is used to obtain the programming voltage input by the input / output module 120 (for example, Figure 2 The VFSBLN signal shown in FIG1 is used as the voltage monitoring signal, and the electric fuse is programmed according to the control signal of the control module 130, and the formed voltage monitoring signal is sent to the analog voltage module 150.

[0046] The voltage monitoring signal (e.g., FUSE_MONI signal) generated by the electric fuse module 160 is connected to the analog voltage module 150. The analog voltage module 150 can send the basic clock frequency OSC and the reference voltage VREF to the electric fuse module 160. Using the test chip TK, in addition to testing the performance of the core memory module 110, the performance of the electric fuse module 160 can also be tested to indirectly obtain information on whether the electric fuse module formed in the chip area 10 is qualified. As needed, in some embodiments, the electric fuse module 160 can perform bidirectional signal transmission with the data channel module 140. For example, the data channel module 140 can transmit test data (test bit) (e.g., Figure 2 DINRTL<7:0> signal shown in FIG. 1 ) is directly sent to the electrical fuse module 160 via the control module 130 to simulate the electrical fuse programming effect. The electrical fuse module 160 can program the result of the fuse element (for example, Figure 2 The SOUT<7:0> signals shown in FIG. 1 are sent to the data channel module 140 for verification.

[0047] like Figure 2 As shown, as an example, the plurality of pads may include pads named VFSBLN (providing a blown electric fuse voltage to the electric fuse module 160), PAD_CSB (asynchronous interrupt signal), PAD_SI (for test data input), PAD_SCLK (providing a clock signal), and PAD_HRSTB (providing a control signal). The test result of the test chip TK is output, for example, through a pad named PAD_SO. Figure 3The multiple pads in the input / output module 120 may include multiple first pads 121a for detecting the analog voltage generated by the above-mentioned low-dropout linear regulator and / or charge pump and multiple second pads 121b for detecting the circuit connection function and read / write performance of the core storage module 110. As needed, the input / output module 120 may also include pads with other functions. The multiple second pads 121b may include pads serving as power input terminals and pads serving as data interfaces. The test chip TK includes a pad area 30, wherein the multiple first pads 121a are, for example, arranged in the first pad area 31, and the multiple second pads 121b are arranged in the second pad area 32. It is worth noting that an external testing machine (not shown) can send the aforementioned test data and test instructions by inserting a probe into the second pad 121b of the test chip TK on the memory wafer structure 100. The probe can then read the output test results from the second pad 121b of the test chip TK on the memory wafer structure 100 to determine whether the read and write functions and circuit connection performance of the memory device array in the memory unit of the chip area 10 are normal. By detecting the signal on the first pad 121a, it can be determined whether the analog voltage module 150 (such as the low-dropout linear regulator and / or charge pump for providing the operating voltage of the memory device array in the core memory module 110) and the corresponding analog voltage module ("corresponding" means the corresponding low-dropout linear regulator and / or charge pump using the same circuit design as the analog voltage module 150) in the memory unit of the chip area 10 is functioning normally.

[0048] After receiving the instruction input through the pad, the pad ring 122 sends the corresponding signal to other modules in the test chip TK. In this embodiment, the pad ring 122 also has an anti-static function. When the storage wafer structure 100 includes two or more storage device wafers connected in a vertical stack, the cutting area 20 of each storage device wafer is formed with a test chip TK, and the input and output modules 120 in the multiple test chips TK stacked vertically in each layer of storage device wafers can be vertically connected to facilitate inputting signals from the outside to the test chips TK in each layer of storage device wafers and obtaining signals detected by the test chips TK. The input and output modules 120 in different storage device wafers can be vertically connected through TSV bonding paths. The TSV bonding path may include a TSV formed in the storage device wafer to connect the front circuit and the back circuit and a metal bonding structure for connecting two adjacent storage device wafers.

[0049] Reference Figure 2As an example, the control module 130 and the data channel module 140 receive a set of signals from the input / output module 120, including the asynchronous interrupt signal CSB, the clock signal SCLK, and the power-on reset signal POR_RST. The control module 130 generates corresponding control signals based on these input signals. In addition to receiving the set of signals including the asynchronous interrupt signal CSB, the clock signal SCLK, and the power-on reset signal POR_RST, the data channel module 140 also receives the input data signal SI from the input / output module 120, control signals from the control module 130, and feedback data signals (e.g., DOUT<127:0>) from the core memory module 110. Furthermore, the data channel module 140 can, for example, perform serial-to-parallel conversion on the serial data transmitted in the input data signal SI to generate parallel input data signals (e.g., DIN<127:0>) output to the core memory module 110. It can also perform parallel-to-serial conversion on the parallel data transmitted in the feedback data signal (e.g., DOUT<127:0>) to generate serial output signals TOIO output to the input / output module 120.

[0050] The storage wafer structure 100 in the embodiment of the present invention is formed with a test chip TK in the cutting area 20. In the test chip TK, the core storage module 110 replicates at least a portion of the storage device array in the storage unit of the chip area 10. Combined with the input and output module 120, the control module 130, the data channel module 140, the analog voltage module 150 and the electric fuse module 160, the storage chip detection function can be realized. Before the storage wafer structure 100 is bonded to the logic circuit wafer, the test chip TK is used for testing, which can indirectly detect the performance and yield of the storage unit of the chip area 10. Therefore, the storage wafer structure 100 can be screened by testing the test chip TK, and the storage wafer structure 100 that passes the test can be bonded to the logic circuit wafer again, which helps to improve the yield of the three-dimensional integrated device including the storage wafer structure 100 and the logic circuit wafer, can reduce the probability of poor testing after bonding, and can reduce scrap costs.

[0051] An embodiment of the present invention further relates to a method for forming a three-dimensional integrated device. The method adopts the memory wafer structure 100 described in the above embodiment. For the features of the memory wafer structure 100 , reference may be made to the description of the above embodiment.

[0052] Reference Figure 4The method for forming the three-dimensional integrated device includes the following process: first, executing step S1 to obtain at least one of the above-mentioned storage wafer structures 100; then, executing step S2, by testing the test chip TK on the storage wafer structure 100, estimating the yield of the storage unit of the chip area 10 of the storage wafer structure 100, and screening out the storage wafer structures 100 that pass the test; then, executing step S3, using the storage wafer structures 100 that pass the test to bond and interconnect with the logic circuit wafer.

[0053] When testing the memory wafer structure 100 using the test chip TK in step S2, at least one of the core memory module 110, the analog voltage module 150, and the electrical fuse module 160 may be tested as needed. By testing the read and write performance, analog voltage module functionality, and circuit connection performance of the test chip TK, the performance and yield of the memory cells in the chip area 10 can be indirectly tested. As an example, in one embodiment, the test results of multiple test chips TK are used to calculate the yield of the multiple test chips TK and use it as the yield of the memory cells in the memory wafer structure 100. When at least one test chip TK passes the test or the yield of multiple test chips TK is greater than a set value, the memory wafer structure 100 is determined to have passed the test and can be bonded and interconnected with the logic circuit wafer.

[0054] In the method for forming a three-dimensional integrated device of an embodiment of the present invention, before bonding the storage wafer structure 100 to the logic circuit wafer, the yield of the storage unit in the chip area 10 of the storage wafer structure 100 is inferred by testing the test chip TK on the storage wafer structure 100, and the storage wafer structure 100 that passes the test is screened out, which helps to improve the yield of the three-dimensional integrated device including the storage wafer structure 100 and the logic circuit wafer, and can reduce scrap costs.

[0055] The above description is only a description of the preferred embodiment of the present invention, and does not limit the scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A storage wafer structure, characterized in that: The invention comprises a plurality of chip areas and a cutting area located around each of the chip areas, wherein each chip area is formed with a memory chip, each memory chip includes a plurality of memory cells including a memory device array, and the cutting area is formed with a test chip, wherein the test chip includes: a core memory module comprising a memory device array, wherein the memory device array in the core memory module is replicated in at least a portion of the memory device array in one of the memory cells; an input / output module, configured to connect an external signal to the test chip and output a signal detected by the test chip, so as to at least detect the circuit connection function and read / write performance of the core storage module; A control module, configured to generate a control signal according to input information of the input / output module; a data channel module, configured to form a bidirectional data transmission channel between the input / output module and the core storage module according to a control signal of the control module; and An electric fuse module is copied to the electric fuse module inside the storage unit. In the test chip, the electric fuse module is used to obtain the programming voltage input by the input / output module and program the electric fuse according to the control signal of the control module. The electric fuse module also sends the result of programming the fuse element to the data channel module for verification.

2. The storage wafer structure according to claim 1, wherein: The amount of data that can be stored in the memory device array of the core memory module is less than or equal to the amount of data that can be stored in the memory device array of one of the memory units.

3. The memory wafer structure according to claim 1, wherein: The core memory module and the memory unit further include local sense amplifiers corresponding to the memory device arrays therein; the control module includes a write controller, a read controller, a row decoder, and a column decoder.

4. The memory wafer structure according to claim 1, wherein: The test chip further includes: The analog voltage module includes a low voltage difference linear regulator and / or a charge pump replicated in the storage unit, and is used to provide the core storage module with the voltage required for the operation of the corresponding storage device array.

5. The storage wafer structure according to claim 4, wherein: The electrical fuse module sends the formed voltage monitoring signal to the analog voltage module.

6. The storage wafer structure according to claim 5, wherein: The input-output module includes a plurality of pads and a pad ring connected to the plurality of pads, wherein the plurality of pads connect the external signal to the test chip, wherein the external signal is used to test at least one of the core storage module, the analog voltage module and the electric fuse module, and the plurality of pads output the test results to determine whether the storage unit in the chip area is qualified.

7. The memory wafer structure according to claim 1, wherein: The input-output module includes a plurality of solder pads and a solder pad ring connected to the plurality of solder pads, and the plurality of solder pads connect the external signals to the test chip; wherein the external signals include test instructions and test data for testing the test chip, and by writing the test data into the core storage module and then reading it out, the plurality of solder pads output the test results to determine whether the storage unit in the chip area is qualified.

8. The memory wafer structure according to claim 1, wherein: The control module and the data channel module both receive a group of signals including asynchronous interrupt signals, clock signals and power-on reset signals from the input and output module; the data channel module also receives input data signals from the input and output module, control signals from the control module and feedback data signals from the core storage module.

9. The memory wafer structure according to claim 8, wherein: The data channel module performs serial-to-parallel conversion on the serial data transmitted by the input data signal to form a parallel input data signal output to the core storage module, and also performs parallel-to-serial conversion on the parallel data transmitted by the feedback data signal to form a serial output signal output to the input-output module.

10. The memory wafer structure according to any one of claims 1 to 9, wherein: The memory wafer structure includes one memory device wafer or two or more memory device wafers that are vertically stacked and bonded.

11. The memory wafer structure according to claim 10, wherein: When the storage wafer structure includes two or more storage device wafers that are vertically stacked and connected, the test chip is formed in the cutting area of ​​each storage device wafer, and the input and output modules in the multiple test chips that are respectively located in each layer of the storage device wafer and stacked vertically are vertically connected.

12. A method for forming a three-dimensional integrated device, characterized in that: include: Obtain at least one storage wafer structure according to any one of claims 1 to 11; By testing the test chip on the storage wafer structure, the yield rate of the storage unit in the chip area of ​​the storage wafer structure is estimated, and the storage wafer structure that has passed the test is screened out; as well as The memory wafer structure that has passed the test is bonded and interconnected with a logic circuit wafer.

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