Intelligent edge computing cooperative processing system based on integrated circuit

Abstract

The invention relates to the technical field of edge computing, and discloses an intelligent edge computing co-processing system based on an integrated circuit, which comprises a heterogeneous computing cluster module, a hardware computing unit set, a multi-core control processor based on RISC-V, a programmable pulse tensor computing array and a reconfigurable engine oriented to streaming processing, according to the intelligent edge computing cooperative processing system based on the integrated circuit, zero-delay data exchange is realized through silicon intermediate layer integration of the heterogeneous computing cluster module and a snakelike data channel, and traditional bus arbitration delay is eliminated through real-time operation code analysis and optimal optical communication path mapping of the hardware task routing matrix (TRF) module; the priority path distribution of the task scheduling subsystem is synchronously coordinated with the time-sensitive task, so that the collaborative efficiency of the computing unit is improved in multiple dimensions, the non-blocking transmission of the high-priority task is ensured, and the effect of enhancing the overall processing capability and response speed of the intelligent edge computing is achieved.

Description

Technical Field

[0001] This invention relates to the field of edge computing technology, specifically to an intelligent edge computing collaborative processing system based on integrated circuits. Background Technology

[0002] With the rapid development of IoT, 5G / 6G communication, and AI technologies, the data generated by massive terminal devices is growing explosively. Traditional cloud computing models, due to issues such as high data transmission latency, large bandwidth consumption, and privacy risks, are unable to meet the stringent real-time requirements of application scenarios. Against this backdrop, edge computing has emerged. It refers to an open platform that integrates core capabilities of network, computing, storage, and applications at the network edge, close to the source of objects or data, to provide edge intelligence services locally, thereby meeting the key needs of industry digitalization in areas such as agile connectivity, real-time business, data optimization, application intelligence, and security and privacy protection.

[0003] In existing intelligent edge computing collaborative processing systems based on integrated circuits, there is a significant delay in data transmission between computing units. Traditional interconnection methods are difficult to achieve efficient data exchange, resulting in low efficiency and slow overall response speed when multiple units are collaboratively processing. Therefore, we urgently need an intelligent edge computing collaborative processing system based on integrated circuits. Summary of the Invention

[0004] To address the aforementioned technical shortcomings, the present invention aims to provide an intelligent edge computing collaborative processing system based on integrated circuits, which significantly enhances the overall processing capability and response speed of intelligent edge computing by integrating various modules.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0006] An integrated circuit-based intelligent edge computing collaborative processing system includes:

[0007] Heterogeneous computing cluster module: A collection of hardware computing units consisting of a RISC-V-based multi-core control processor, a programmable systolic tensor computing array, and a reconfigurable engine oriented towards streaming processing;

[0008] Hardware Task Routing Matrix (TRF) module: A silicon-based photonic interconnect layer connecting the various units of the heterogeneous computing cluster;

[0009] Dynamic power management module: provides voltage and frequency island circuits for partitioned power supply to the heterogeneous computing cluster;

[0010] Task scheduling subsystem: directly controls the TRF module to parse computing tasks in real time, generate data stream execution sequences, and configure physical transmission paths;

[0011] Security Subsystem: A hardware security component integrating the memory and computing bus of the heterogeneous computing cluster, providing task-level key management, memory data encryption, and computing output verification functions;

[0012] Chip-level packaging structure: a physical carrier for integrating the modules through three-dimensional vertical stacking, including high-density interconnect channels and embedded heat dissipation structure;

[0013] Cloud-edge collaborative communication interface: A physical communication port integrating the aforementioned chip-level packaging structure, supporting remote bit stream configuration and edge node control signal transmission;

[0014] Data communication and power transmission between modules are achieved through a physical interconnection layer.

[0015] Preferably, the programmable systolic tensor computation array includes:

[0016] A reconfigurable computing unit array that supports dynamic switching of multi-precision operation modes, with each computing unit integrating mixed-precision arithmetic logic circuits;

[0017] The computing units are interconnected through a bidirectional serpentine topology data channel, which uses multi-layer metal wiring to achieve signal transmission.

[0018] An embedded in-memory computing storage block consists of non-volatile memory cells and adjacent computing circuitry.

[0019] Preferably, the hardware task routing matrix (TRF) module further includes:

[0020] Real-time task opcode parsing circuit: a dedicated integrated circuit consisting of a hardware decoder and a feature extraction logic gate array;

[0021] Inter-core communication path mapping memory: a physical storage unit that uses non-volatile storage medium to store the optimal path mapping table;

[0022] Photonic routing engine: contains optical signal processing components including micro-ring resonator arrays and multi-wavelength laser sources.

[0023] Preferably, the dynamic power management module further includes:

[0024] Processor instruction cycle monitoring sensor: Integrated into the instruction pipeline monitoring circuit of each computing core;

[0025] Multi-level power consumption state control circuit: clock gating and voltage regulation unit for triggering sleep mode;

[0026] Charge recovery storage unit: an energy storage device consisting of a MOS capacitor array and a reverse energy conversion circuit.

[0027] Preferably, the task scheduling subsystem includes:

[0028] Atomic operation decomposition unit: A hardware state machine that parses computational tasks into basic operation flows;

[0029] Data stream execution sequence generator: a data dependency parsing circuit implemented using a hardware description language;

[0030] Physical transmission path configuration interface: connects the register configuration channel and signal routing switch array of the TRF module.

[0031] Preferably, the task scheduling subsystem includes:

[0032] High-priority channel allocator: Hardware arbitration circuitry that reserves dedicated physical bandwidth for real-time tasks;

[0033] Transmission delay guarantee unit: Quality of service control logic gate array integrated into the photonic interconnect layer;

[0034] Time-sensitive task synchronization circuit: a distributed coordination module based on hardware timestamps.

[0035] Preferably, the security subsystem includes:

[0036] Task-level key management unit: Dynamic key generation circuit based on physically non-clonable functions;

[0037] Memory data encryption engine: AES-256 encryption / decryption module integrated into the memory controller;

[0038] Calculation output verification circuit: CRC verification unit integrated into the pulse array output bus.

[0039] Preferably, the chip-level packaging structure includes:

[0040] Vertical stacking architecture: Achieving three-dimensional integration of heterogeneous computing clusters and high-bandwidth memory through a silicon interposer layer;

[0041] High-density interconnect structure: microbump array and through-silicon via layer connecting computing units and memory;

[0042] Integrated cooling module: microfluidic cooling channels and thermal interface material layer embedded in the package.

[0043] Preferably, the cloud-edge collaborative communication interface includes:

[0044] Edge node execution unit: an embedded hardware module containing sensor interfaces and communication modules;

[0045] Cloud configuration update interface: The physical communication port for receiving remote bitstream configuration;

[0046] Hardware architecture reconfiguration unit: parses the bitstream and reconstructs the FPGA circuitry of the computing unit.

[0047] Compared with the prior art, the beneficial effects achieved by the present invention are:

[0048] First, this invention achieves zero-latency data exchange through silicon interposer integration and serpentine data channels in heterogeneous computing cluster modules. Real-time opcode parsing and optimal optical communication path mapping in the hardware task routing matrix (TRF) module eliminate the latency of traditional bus arbitration. Priority path allocation and time-sensitive task synchronization coordination in the task scheduling subsystem improve the collaborative efficiency of computing units in multiple dimensions, ensure non-blocking transmission of high-priority tasks, and enhance the overall processing capability and response speed of intelligent edge computing.

[0049] Secondly, this invention utilizes the processor instruction cycle monitoring, low-load sleep control, and charge recovery storage of the dynamic power management module to achieve refined dynamic management of system energy consumption. It shuts down idle units to reduce ineffective energy consumption under low load, and captures, stores, and releases electrical energy through the charge recovery unit, effectively reducing the overall power consumption of the system and improving energy utilization efficiency, thus achieving the effect of adapting to the low power consumption requirements of edge computing scenarios.

[0050] Third, this invention constructs a hardware-level security protection system covering the entire process from task execution to data transmission by using a physical non-clonable function dynamic key generation, memory access channel encryption, real-time verification of calculation results, and optical isolation protection in case of anomalies in the security subsystem. This prevents unauthorized access and data tampering, ensures the security of sensitive data processing and the reliability of critical task execution, and enhances the system's reliable processing capabilities in complex edge environments. Attached Figure Description

[0051] Figure 1 This is a schematic diagram of the rectification process of the present invention; Detailed Implementation

[0052] The specific embodiments of the present invention will now be described in further detail with reference to the accompanying drawings. Specific Implementation Method 1

[0054] The following is a specific implementation of an intelligent edge computing collaborative processing system based on integrated circuits.

[0055] Please see Figure 1 An integrated circuit-based intelligent edge computing collaborative processing system includes:

[0056] Heterogeneous computing cluster module: A collection of hardware computing units consisting of a RISC-V-based multi-core control processor, a programmable systolic tensor computing array, and a reconfigurable engine oriented towards streaming processing;

[0057] Hardware Task Routing Matrix (TRF) module: A silicon-based photonic interconnect layer connecting the various units of the heterogeneous computing cluster;

[0058] Dynamic power management module: provides voltage and frequency island circuits for partitioned power supply to the heterogeneous computing cluster;

[0059] Task scheduling subsystem: directly controls the TRF module to parse computing tasks in real time, generate data stream execution sequences, and configure physical transmission paths;

[0060] Security Subsystem: A hardware security component integrating the memory and computing bus of the heterogeneous computing cluster, providing task-level key management, memory data encryption, and computing output verification functions;

[0061] Chip-level packaging structure: a physical carrier for integrating the modules through three-dimensional vertical stacking, including high-density interconnect channels and embedded heat dissipation structure;

[0062] Cloud-edge collaborative communication interface: A physical communication port integrating the aforementioned chip-level packaging structure, supporting remote bit stream configuration and edge node control signal transmission;

[0063] Data communication and power transmission between modules are achieved through a physical interconnection layer.

[0064] Through the above technical solution, the heterogeneous computing cluster module consists of a RISC-V-based multi-core control processor, a programmable systolic tensor computing array, and a reconfigurable engine oriented towards streaming processing. Physical integration is achieved through a silicon interposer. The RISC-V control core uses a hardware interrupt mechanism to schedule the reconfigurable engine's operating mode switching. The programmable systolic array and the reconfigurable engine establish a direct physical connection through a serpentine data channel to achieve zero-latency data exchange. The silicon-based photonic interconnect layer of the hardware task routing matrix (TRF) module is composed of a silicon photonic waveguide layer. A dedicated feature analysis circuit identifies task opcodes in real time and maps them to the optimal optical communication path, eliminating traditional bus arbitration latency. The dynamic power management module divides the system into independent voltage and frequency islands, and load monitoring sensors continuously collect the state of the computing core's instruction cycle. Under low load, a sleep control circuit is triggered to shut down idle processes. The system integrates a set-top unit and a charge recovery unit to store the released electrical energy in a MOS capacitor array. The task scheduling subsystem analyzes the computing tasks in real time, generates a data stream execution sequence, and configures the physical transmission path of the TRF module. The hardware security components of the security subsystem are integrated into the memory and computing bus of the heterogeneous computing cluster, providing task-level key management, memory data encryption, and computing output verification. The chip-level packaging structure integrates each module through three-dimensional vertical stacking. High-density interconnect channels and embedded heat dissipation structures ensure signal transmission and heat dissipation. The embedded hardware module of the cloud-edge collaborative communication interface directly connects to the sensing device, supports remote bit stream configuration and edge node control signal transmission. Each module realizes data communication and power transmission through the physical interconnect layer, thereby achieving multi-core efficient collaborative computing, dynamic energy consumption optimization, and safe and reliable intelligent edge computing collaborative processing.

[0065] Specifically, the programmable systolic tensor computation array includes:

[0066] A reconfigurable computing unit array that supports dynamic switching of multi-precision operation modes, with each computing unit integrating mixed-precision arithmetic logic circuits;

[0067] The computing units are interconnected through a bidirectional serpentine topology data channel, which uses multi-layer metal wiring to achieve signal transmission.

[0068] An embedded in-memory computing storage block consists of non-volatile memory cells and adjacent computing circuitry.

[0069] Through the above technical solution, each computing unit in the reconfigurable computing unit array integrates mixed-precision arithmetic logic circuits. By configuring registers, dynamic switching between single-precision, half-precision, or INT8 multi-precision operation modes can be achieved. The computing units are interconnected through a bidirectional serpentine topology data channel. This channel uses multi-layer metal wiring, and adjacent computing units are connected by short-distance metal wires to reduce signal delay. The embedded in-memory computing storage block is tightly integrated with non-volatile memory units and adjacent computing circuits. Data is directly calculated near the storage unit, which greatly reduces data handling overhead and improves the flexibility and efficiency of tensor computing.

[0070] Specifically, the hardware task routing matrix (TRF) module also includes:

[0071] Real-time task opcode parsing circuit: a dedicated integrated circuit consisting of a hardware decoder and a feature extraction logic gate array;

[0072] Inter-core communication path mapping memory: a physical storage unit that uses non-volatile storage medium to store the optimal path mapping table;

[0073] Photonic routing engine: contains optical signal processing components including micro-ring resonator arrays and multi-wavelength laser sources.

[0074] Through the above technical solution, the real-time task opcode parsing circuit is composed of a dedicated integrated circuit consisting of a hardware decoder and a feature extraction logic gate array. It performs parallel decoding on the input task opcode and quickly identifies the task type and data dependency. The inter-core communication path mapping memory adopts non-volatile storage media such as phase-change memory and pre-stores the optimal path mapping table for quick lookup during task routing. The photonic routing engine includes a micro-ring resonator array and a multi-wavelength laser source. By adjusting the resonant frequency of the micro-ring resonator through thermo-optic or electro-optic effects, it realizes the routing control of optical signals of specific wavelengths, thereby achieving efficient task routing and inter-core communication.

[0075] Specifically, the dynamic power management module further includes:

[0076] Processor instruction cycle monitoring sensor: Integrated into the instruction pipeline monitoring circuit of each computing core;

[0077] Multi-level power consumption state control circuit: clock gating and voltage regulation unit for triggering sleep mode;

[0078] Charge recovery storage unit: an energy storage device consisting of a MOS capacitor array and a reverse energy conversion circuit.

[0079] Through the above technical solution, the processor instruction cycle monitoring sensor is integrated into the instruction pipeline of each computing core to collect the instruction execution frequency of the computing core in real time. The multi-level power consumption status control circuit includes a clock gating and voltage regulation unit, which dynamically adjusts the clock frequency and voltage according to the status collected by the load monitoring sensor. It triggers a sleep mode under low load. The charge recovery storage unit consists of a MOS capacitor array and a reverse energy conversion circuit. It collects the released electrical energy when the computing unit is idle and releases it to supplement power supply under high load, thereby realizing dynamic management of system power consumption, reducing energy consumption and improving energy utilization efficiency.

[0080] Specifically, the task scheduling subsystem includes:

[0081] Atomic operation decomposition unit: A hardware state machine that parses computational tasks into basic operation flows;

[0082] Data stream execution sequence generator: a data dependency parsing circuit implemented using a hardware description language;

[0083] Physical transmission path configuration interface: connects the register configuration channel and signal routing switch array of the TRF module.

[0084] Through the above technical solution, the atomic operation decomposition unit is a hardware state machine that parses the computation task into basic operation flows, realizes the fine-grained decomposition of the task, and the data flow execution sequence generator implements the data dependency parsing circuit based on the hardware description language. It generates the optimal data flow execution sequence according to the decomposed basic operation flow. The physical transmission path configuration interface is connected to the register configuration channel and signal routing switch array of the TRF module to dynamically configure the physical transmission path, thereby improving task scheduling efficiency and data transmission performance.

[0085] Specifically, the task scheduling subsystem includes:

[0086] High-priority channel allocator: Hardware arbitration circuitry that reserves dedicated physical bandwidth for real-time tasks;

[0087] Transmission delay guarantee unit: Quality of service control logic gate array integrated into the photonic interconnect layer;

[0088] Time-sensitive task synchronization circuit: a distributed coordination module based on hardware timestamps.

[0089] Through the above technical solutions, the high-priority channel allocator is a hardware arbitration circuit that reserves dedicated physical bandwidth for real-time tasks, ensuring the bandwidth requirements of real-time tasks. The transmission delay guarantee unit is a service quality control logic gate array integrated into the photonic interconnect layer, ensuring the timeliness of data transmission. The time-sensitive task synchronization circuit is a distributed coordination module based on hardware timestamps, realizing the synchronization of time-sensitive tasks and improving the system's processing capability and reliability for real-time tasks.

[0090] Specifically, the security subsystem includes:

[0091] Task-level key management unit: Dynamic key generation circuit based on physically non-clonable functions;

[0092] Memory data encryption engine: AES-256 encryption / decryption module integrated into the memory controller;

[0093] Calculation output verification circuit: CRC verification unit integrated into the pulse array output bus.

[0094] Through the above technical solution, the task-level key management unit is a dynamic key generation circuit based on a physically non-clonable function, which generates a unique task-level key. The memory data encryption engine is integrated into the memory controller and is an AES-256 encryption and decryption module, which performs encryption protection during data reading and writing. The calculation output verification circuit is a CRC verification unit integrated into the pulse array output bus, which performs real-time verification of the calculation results. Once an anomaly is detected, the optical isolator is immediately driven to cut off the physical detection path of the unauthorized core, ensuring the security of the system and the integrity of the data.

[0095] Specifically, the chip-level packaging structure includes:

[0096] Vertical stacking architecture: Achieving three-dimensional integration of heterogeneous computing clusters and high-bandwidth memory through a silicon interposer layer;

[0097] High-density interconnect structure: microbump array and through-silicon via layer connecting computing units and memory;

[0098] Integrated cooling module: microfluidic cooling channels and thermal interface material layer embedded in the package.

[0099] Through the above technical solutions, the vertical stacking architecture achieves three-dimensional integration of heterogeneous computing clusters and high-bandwidth memory through a silicon interposer, shortening the signal transmission distance. The high-density interconnect structure uses a micro-bump array and a silicon via layer to connect computing units and memory, providing a high-speed data transmission channel. The microfluidic cooling channel and thermal interface material layer of the integrated cooling module are embedded in the package to quickly remove heat from the package, improving the chip's integration and performance, and ensuring system reliability.

[0100] Specifically, the cloud-edge collaborative communication interface includes:

[0101] Edge node execution unit: an embedded hardware module containing sensor interfaces and communication modules;

[0102] Cloud configuration update interface: The physical communication port for receiving remote bitstream configuration;

[0103] Hardware architecture reconfiguration unit: parses the bitstream and reconstructs the FPGA circuitry of the computing unit.

[0104] Through the above technical solution, the edge node execution unit is an embedded hardware module containing sensor interfaces and communication modules, which directly connects to sensing devices to collect and preprocess data. The cloud configuration update interface is a physical communication port that receives remote bit stream configurations. It receives bit streams containing calculation precision mode configuration instructions, optical routing policy tables, and power consumption thresholds. The hardware architecture reconfiguration unit is an FPGA circuit that parses the bit stream and reconstructs the computing unit. After parsing the bit stream, it dynamically reconstructs the hardware working state and simultaneously starts a self-evolutionary feedback circuit to continuously collect the computing core status and task latency characteristics, and encrypts and sends them back to the cloud to drive policy optimization, thereby realizing the collaborative work between the edge node and the cloud and the flexible configurability of the system.

[0105] Working Principle: After system startup, the heterogeneous computing cluster module physically integrates the RISC-V multi-core control processor, programmable systolic tensor computing array, and reconfigurable engine through a silicon interposer. The RISC-V control core schedules the reconfigurable engine's operating mode switching via hardware interrupt mechanisms. The programmable systolic array and the reconfigurable engine achieve zero-latency data exchange through a serpentine data channel. Simultaneously, the dedicated feature parsing circuit of the hardware task routing matrix (TRF) module identifies task opcodes in real time. Combined with the optimal path table stored in the inter-core communication path mapping memory, the micro-ring resonator array of the photonic routing engine and the multi-wavelength laser source construct an optical communication path, eliminating the latency of traditional bus arbitration. The task scheduling subsystem first decomposes complex tasks into basic operation flows through atomic operation decomposition units. The data flow execution sequence generator generates priority execution sequences based on data dependencies. The physical transmission path configuration interface configures the routing switches of the TRF module accordingly, allocating dedicated optical transmission channels for high-priority tasks. The time-sensitive task synchronization circuit achieves distributed coordination through hardware timestamps. The dynamic power management module processes... The processor instruction cycle monitoring sensor continuously collects the computing core status. The multi-level power consumption status control circuit triggers a sleep mode and shuts down idle units under low load. The charge recovery storage unit simultaneously captures and releases electrical energy and stores it in the MOS capacitor array to achieve dynamic energy consumption optimization. In the security subsystem, the task-level key management unit generates dynamic keys based on physically unclonable functions, the memory data encryption engine encrypts the memory access channel, and the verification circuit at the output of the pulsating array verifies the calculation results in real time. In case of an anomaly, it drives the opto-isolator to cut off unauthorized access paths. The chip-level packaging structure shortens the signal transmission distance through three-dimensional vertically stacked silicon interposers, high-density micro-bump arrays, and through-silicon vias. The integrated cooling module quickly dissipates heat. The edge node execution unit of the cloud-edge collaborative communication interface is directly connected to the sensing device. The bit stream generated by the cloud configuration engine is parsed by the hardware architecture reconfiguration unit and the hardware state is reconstructed. The self-evolutionary feedback circuit collects running data, encrypts it, and sends it back to the cloud to optimize the configuration strategy. Each module realizes data and power transmission through the physical interconnect layer, ultimately achieving efficient collaboration, low-power operation, security, reliability, and flexible adaptation of intelligent edge computing.

[0106] Although specific embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these specific embodiments without departing from the principles and spirit, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A smart edge computing collaborative processing system based on integrated circuits, characterized in that: include: Heterogeneous computing cluster module: A collection of hardware computing units consisting of a RISC-V-based multi-core control processor, a programmable systolic tensor computing array, and a reconfigurable engine oriented towards streaming processing; Hardware Task Routing Matrix (TRF) module: A silicon-based photonic interconnect layer connecting the various units of the heterogeneous computing cluster; Dynamic power management module: provides voltage and frequency island circuits for partitioned power supply to the heterogeneous computing cluster; Task scheduling subsystem: directly controls the TRF module to parse computing tasks in real time, generate data stream execution sequences, and configure physical transmission paths; Security Subsystem: A hardware security component integrating the memory and computing bus of the heterogeneous computing cluster, providing task-level key management, memory data encryption, and computing output verification functions; Chip-level packaging structure: a physical carrier for integrating the modules through three-dimensional vertical stacking, including high-density interconnect channels and embedded heat dissipation structure; Cloud-edge collaborative communication interface: A physical communication port integrating the aforementioned chip-level packaging structure, supporting remote bit stream configuration and edge node control signal transmission; Data communication and power transmission between modules are achieved through a physical interconnection layer.

2. The intelligent edge computing collaborative processing system based on integrated circuits according to claim 1, characterized in that: The programmable systolic tensor computation array includes: A reconfigurable computing unit array that supports dynamic switching of multi-precision operation modes, with each computing unit integrating mixed-precision arithmetic logic circuits; The computing units are interconnected through a bidirectional serpentine topology data channel, which uses multi-layer metal wiring to achieve signal transmission. An embedded in-memory computing storage block consists of non-volatile memory cells and adjacent computing circuitry.

3. The intelligent edge computing collaborative processing system based on integrated circuits according to claim 1, characterized in that: The hardware task routing matrix (TRF) module also includes: Real-time task opcode parsing circuit: a dedicated integrated circuit consisting of a hardware decoder and a feature extraction logic gate array; Inter-core communication path mapping memory: a physical storage unit that uses non-volatile storage medium to store the optimal path mapping table; Photonic routing engine: contains optical signal processing components including micro-ring resonator arrays and multi-wavelength laser sources.

4. The intelligent edge computing collaborative processing system based on integrated circuits according to claim 1, characterized in that: The dynamic power consumption management module further includes: Processor instruction cycle monitoring sensor: Integrated into the instruction pipeline monitoring circuit of each computing core; Multi-level power consumption state control circuit: clock gating and voltage regulation unit for triggering sleep mode; Charge recovery storage unit: an energy storage device consisting of a MOS capacitor array and a reverse energy conversion circuit.

5. The intelligent edge computing collaborative processing system based on integrated circuits according to claim 1, characterized in that: The task scheduling subsystem includes: Atomic operation decomposition unit: A hardware state machine that parses computational tasks into basic operation flows; Data stream execution sequence generator: a data dependency parsing circuit implemented using a hardware description language; Physical transmission path configuration interface: connects the register configuration channel and signal routing switch array of the TRF module.

6. The intelligent edge computing collaborative processing system based on integrated circuits according to claim 1, characterized in that: The task scheduling subsystem includes: High-priority channel allocator: Hardware arbitration circuitry that reserves dedicated physical bandwidth for real-time tasks; Transmission delay guarantee unit: Quality of service control logic gate array integrated into the photonic interconnect layer; Time-sensitive task synchronization circuit: a distributed coordination module based on hardware timestamps.

7. The intelligent edge computing collaborative processing system based on integrated circuits according to claim 1, characterized in that: The security subsystem includes: Task-level key management unit: Dynamic key generation circuit based on physically non-clonable functions; Memory data encryption engine: AES-256 encryption / decryption module integrated into the memory controller; Calculation output verification circuit: CRC verification unit integrated into the pulse array output bus.

8. The intelligent edge computing collaborative processing system based on integrated circuits according to claim 1, characterized in that: The chip-level packaging structure includes: Vertical stacking architecture: Achieving three-dimensional integration of heterogeneous computing clusters and high-bandwidth memory through a silicon interposer layer; High-density interconnect structure: microbump array and through-silicon via layer connecting computing units and memory; Integrated cooling module: microfluidic cooling channels and thermal interface material layer embedded in the package.

9. The intelligent edge computing collaborative processing system based on integrated circuits according to claim 1, characterized in that: The cloud-edge collaborative communication interface includes: Edge node execution unit: an embedded hardware module containing sensor interfaces and communication modules; Cloud configuration update interface: The physical communication port for receiving remote bitstream configuration; Hardware architecture reconfiguration unit: parses the bitstream and reconstructs the FPGA circuitry of the computing unit.

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