Fast generating method of user-customizable PLD (programmable logic device) layouts

Abstract

The invention belongs to the technical field of electronic design automation and particularly relates to a fast generating method of a user-customizable PLD (programmable logic device) layouts. The fast generating method includes: preparing unit layouts and building a configuration file for each unit layout; calculating scale of each unit layout; splicing the unit layouts; and reserving customized layout shapes. On the basis of the existing unit layout library, layout files of optionally designed scales can be generated fast and performance of the layouts generated is similar to that of manually customized layouts. The layouts generated by the method has the advantages that scales of the generated programmable logic array layouts are customizable, namely a user can assign the scales of layout arrays, areas can be reserved automatically on the layouts according to the layout shape requirements set by a user, and other IP (intellectual property) cores can be embedded in the programmable logic array layouts conveniently.

Description

technical field [0001] The invention belongs to the technical field of electronic design automation, and in particular relates to a method for quickly generating a programmable logic array layout supporting user customization. Background technique [0002] Field Programmable Gate Array (Field Programmable Gate Array, FPGA), which is in Programmable Array Logic (Programmable Array Logic, PAL), General Array Logic (Generic Array Logic, GAL), Complex Programmable Logic Device (Complex Programmable Logic Device , CPLD) and other programmable devices based on the further development of the product. It first appeared as a way to verify the prototype function of an application specific integrated circuit (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of original programmable device gates [1]. [0003] Due to the short FPGA design cycle, fast time to market, low Non-Recursive Engineering (NRE), and dynami...

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Problems solved by technology

[0004]Different SoC designs often have different requirements for logic resources, which results in a waste of resources if the FPGA IP core is too large, and if the FPGA IP is too small Not enough cores to meet resource requirements

Therefore, a kind of FPGA layout generation tool that can be required according to user scale is very necessary, before the tool of the present invention proposes, some research groups of the University of Toronto have done some FPGA layout generation tools [4], but this tool generates from scratch The layout does not make good use of the advantages of artificially customized high-efficiency layouts. It takes a long time to generate layouts, and the efficiency of the generated layouts is low, and there is still a long distance from commercial requirements.

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