274 results about "Electronic design automation" patented technology

The invention discloses a PCB component layout method, device and equipment based on a multi-modal large model, and relates to the technical field of electronic design automation, the method comprises the following steps: carrying out quality screening on a plurality of PCB design files which have been laid out to obtain a qualified design file set; constructing a serialized training sample set based on the qualified design file set; each training sample sequence comprises a plurality of training samples arranged according to a layout logic sequence; each training sample comprises multi-modal data representing a current layout state and a real position coordinate of a next component to be laid out; based on the serialized training sample set, training the open-source multi-modal large model to obtain a PCB component layout model; and iteratively generating a layout file of the target PCB based on the netlist file of the target PCB and the PCB component layout model. The method is high in generalization capability and low in cost based on the PCB component layout model trained by the layout data, and can realize rapid layout of components of a new PCB.

The invention discloses a PCB layout optimization method, system and device based on an evolutionary algorithm and a medium, and relates to the field of electronic design automation, and the method comprises the steps: S1, obtaining an initial layout generated by a PCB; s2, judging whether the number of iterations is greater than or equal to the maximum number of iterations; s3, if yes, ending; s4, if not, random disturbance is generated according to the current layout, and a new layout is generated; s5, comparing the new layout with the current layout by adopting an objective function, and judging whether the new layout is superior to the current layout or not; s6, if not, whether the acceptance probability function is larger than a set value or not is judged; s7, if not, returning to S2; s8, if the acceptance probability function is greater than a set value or the new layout is superior to the current layout, taking the new layout as the current layout; and S9, when the current layout is superior to the optimal layout, updating the optimal layout by using the current layout, and returning to S2. According to the method, optimization of the layout of the PCB is realized, and a more ideal layout effect is achieved.

The invention relates to the technical field of electronic design automation, in particular to a coverage rate-based index database management method, coverage rate-based index database management equipment and a storage medium. Meanwhile, extracting design level information in the coverage rate database to establish an index database consisting of a plurality of index tables; when the visual query window initiates a query request, the index database queries the identifier of the target object according to the query request, and processes and updates the target window of the coverage rate visual system according to the identifier in the coverage rate data structure, so that the search efficiency is greatly improved, and the search time is shortened. And the purpose of real-time searching is achieved.

The invention belongs to the field of electronic design automation, and discloses a multi-agent radio frequency circuit netlist generation method and system based on a large language model, and the method comprises the steps: preparing a data set, and constructing a knowledge base; the method comprises the following steps: receiving and analyzing a natural language demand of a user, combining a cue word project and an RAG mechanism, carrying out chained reasoning, introducing a radio frequency design rule, and converting the information into structured parameter information; combining RAG knowledge base retrieval and new topology generation, and fusing PDK process constraints to obtain candidate topologies and a simulation netlist; a simulation tool is called to execute parameter analysis, iterative optimization is conducted on parameters in combination with a closed-loop feedback mechanism, and a final netlist meeting user requirements is obtained. Automatic decomposition, parallel cooperation and high-speed iteration of design tasks are achieved through multi-agent cooperation and in combination with the radio frequency knowledge graph and the RAG; introducing physical constraints to enable the generated topological structure and parameters to meet the physical constraints; and a closed-loop simulation feedback mechanism is fused, so that the dependence on manpower is reduced.

The invention relates to the technical field of electronic design automation, and discloses a standard cell layout legalization method and system based on a graph theory constraint graph, and the method comprises the steps: building a bidirectional directed constraint graph based on an existing layout and a design rule, and building a directed edge between adjacent graph edges according to the design rule; traversing the constraint graph, detecting whether a directed edge which does not meet a constraint condition exists, and if so, identifying the directed edge as a constraint violation edge; for two end points of each constraint violation edge, searching a key path based on a depth-first search algorithm, and determining a maximum movable distance in combination with a greedy strategy; moving the endpoint to a legal position according to the critical path and the maximum movable distance, and updating the position of a related node in the constraint graph; and mapping the position changes of the nodes in the constraint graph back to the corresponding graph edges in the layout, and outputting the legalized layout, so that efficient and automatic repair of design rule violation is realized through the method, and the layout compliance rate and the area optimization effect are remarkably improved.

A method for data center switching fabric path emulation in an electronics design automation (EDA) environment includes generating emulated data center traffic. The method further includes, at a path emulation element, modifying the emulated data center traffic to emulate passing of the emulated data center traffic through a data center switching fabric. The method further includes outputting, by the path emulation element, the modified emulated data center traffic to an EDA emulator emulating an electronics design under test. The method further includes receiving and storing a response of electronics design under test to the modified emulated data center traffic.

The invention relates to the technical field of electronic design automation, and provides a printed circuit board wiring method and device, equipment, a medium and a program, and the method comprises the steps: classifying an obstacle as a pushable object or a non-pushable object; based on the relative position relationship between the initial path and the pushing object, constructing a geometric occupied area of the pushing object, and performing path offset on the pushing object according to the geometric occupied area; in the deviation process, if the distance between any deviated object capable of being pushed and any deviated object not capable of being pushed is smaller than a preset safety distance, further deviation is stopped, and the deviated object capable of being pushed is reversely returned along the deviation track of the object until the distance between the object capable of being pushed and the object not capable of being pushed is larger than or equal to the safety distance; and re-planning a final path of the signal line according to the position of each pushable object after returning, and outputting a wiring result according with a wiring rule. The method is used for optimizing and completing signal path optimization and distribution in an environment with obstacles.

The invention provides a DFT process monitoring method and device, electronic equipment and a storage medium, and belongs to the technical field of DFTs. The DFT process monitoring method comprises the steps that in response to monitoring that execution of a current test task is finished, a process state and a current log file generated in the process of executing the current test task are obtained; determining a target predefined analysis rule corresponding to the type of the EDA tool adopted for executing the current test task through a mapping relation between the type of the EDA tool and the predefined analysis rule; analyzing the current log file through a target predefined analysis rule to obtain semantic keywords; and determining a final execution state of the current test task based on the process state and the semantic keyword. According to the scheme, massive unstructured log files generated by different EDA tools can be analyzed, and the final execution state of each test task can be determined.

The invention relates to a unified PDK interface specification-based conversion method, and relates to the technical field of electronic design automation, and the method comprises the following steps: obtaining commercial PDK data; performing semantic analysis and structure reconstruction on the model file based on a machine learning transfer learning algorithm to generate a standardized intermediate model; according to a unified PDK interface specification, converting the intermediate model into target PDK data conforming to an independent research and development simulation platform format; and automatically importing the target PDK data to the simulation platform through the templated script, and verifying the integrity and consistency of the target PDK data. The method can be applied to a core particle system design process, unified access and co-simulation of the commercial PDK and the open-source PDK are realized, and the design efficiency of an integrated circuit is improved.

The invention relates to a defect analysis and process optimization method based on artificial intelligence multi-mode fusion, and the method comprises the steps: respectively inputting virtual data of a chip or device design layout, an expected process flow and parameters, and an expected electrical performance curve into an image encoder, a process encoder, and an electrical encoder, extracting a corresponding feature vector; performing cross-modal information interaction on the corresponding feature vectors according to a cross attention fusion mechanism; determining a representation image, a defect category, a root cause category and a process parameter correction suggestion; and based on a manufacturing execution system (MES), an electronic design automation (EDA) tool or an equipment interface, process parameters are corrected, and a closed-loop control result from defect analysis to process optimization is obtained. Therefore, the problems of single data dimension, mutual coupling of various defects, influence of background noise, limited machine identification accuracy, overlarge workload of artificial expert judgment and low efficiency are solved.

The invention discloses a circuit netlist conversion method, a circuit netlist conversion control method and a circuit netlist conversion control device. The method comprises the steps that a circuit netlist is obtained and analyzed, netlist intermediate data are constructed, the netlist intermediate data comprise netlist element data and netlist topological data, the netlist element data are used for representing electrical parameters of circuit elements, and the netlist topological data are used for representing the connection relation of the circuit elements; converting the netlist element data into schematic diagram element data according to an element configuration rule of the target electronic design automation tool; determining position information of the circuit elements and routing information between the circuit elements based on the netlist topological data, and generating schematic diagram layout data adaptive to the target electronic design automation tool; and according to the schematic diagram element data and the schematic diagram layout data, generating a circuit schematic diagram file through the target electronic design automation tool. The circuit netlist conversion method has the technical effect of improving the circuit netlist conversion efficiency.

The invention provides a DFT resource configuration prediction method and device, electronic equipment and a storage medium, and belongs to the technical field of electronic design automation, and the method comprises the steps: determining a reference device density based on a process node of a target chip; determining an effective digital logic layout area based on the chip planning area of the target chip and the estimated non-digital logic function region; according to a utilization rate factor corresponding to the physical design constraint of the target chip, correcting the effective digital logic layout area to obtain an available standard cell layout capacity; according to the standard unit layout capacity and the reference device density, generating a time sequence element number prediction interval of the target chip through a logic depth mapping model; and according to the time sequence element number prediction interval, generating testability design DFT architecture configuration parameters of the target chip. The number of chip registers can be quickly and accurately predicted and the DFT architecture configuration parameters can be generated in the early stage of chip design.

The invention relates to the field of electronic design automation, provides a method for semi-automatically processing an EDA (Electronic Design Automation) project file and generating a YOLO format annotation data set, and aims to solve the technical problems of low efficiency and poor precision of the traditional pure manual data annotation data set. According to the main scheme, the method comprises the steps of reading an engineering file of a jia-creative EDA project, analyzing and extracting element information, generating a standardized CSV data format, converting the standardized CSV data format into a label in a YOLO format, calculating normalized bounding box coordinates of elements, and recognizing special original elements and supplementing labeling information in combination with a template matching technology; drawing a bounding box on the schematic diagram image according to a YOLO label, highlighting different element types by using different colors, and generating a visual annotation image; revising and combining the newly generated YOLO label and a preliminary YOLO label generated by the AI model to obtain a label set; then importing into Labelimg for manual correction, and generating a final label set; and training a target detection model by using the final label set, and improving the pre-labeling precision through data set expansion iteration.

The invention belongs to the field of electronic design automation (EDA), and particularly provides a logic comprehensive optimization operator acceleration method, which introduces a screening strategy of a sub-circuit diagram, and improves the optimization efficiency of an operator on the premise of ensuring the optimization quality of the operator. According to the method, the sub-circuit diagrams are classified by using the graph neural network, and the sub-diagrams suitable for operator execution are screened out, so that all the sub-diagrams are prevented from being traversed, and the operator execution speed is increased; in the sub-graph screening, a screening range is set according to the execution sequence of operators, a relatively large screening range is set for the operators executed firstly so as to obtain a better optimization effect, and a relatively small screening range is set for the operators executed later so as to obtain a higher execution speed; in conclusion, the characteristic that the logic comprehensive optimization operator is continuously executed in a sequence mode is utilized, and the operator optimization efficiency is improved on the premise that the operator optimization quality is guaranteed.

The invention relates to the technical field of electronic design automation, in particular to a function coverage rate data compression and storage method, system and device and a storage medium. Collecting the coverage rate of each coverage point or cross coverage and the hit times of each bin subordinate to the coverage point or the cross coverage; acquiring a coverage rate grade and a corresponding data structure; dynamically selecting a target data structure according to the target coverage rate grade of the coverage rate of the target coverage point or the cross coverage; operating a corresponding target data structure through a dynamic storage selector according to the target data structure, wherein the target data structure comprises a flag bit of the current data structure and storage structure data; wherein the storage structure data comprises at least one of the serial number of the bin and the hit frequency of the bin, and the storage overhead is remarkably reduced.

The invention relates to the technical field of electronic design automation, in particular to a network loop detection method based on deep traversal, electronic equipment and a storage medium, and the method comprises the steps: obtaining a node set and an edge set under a target network, constructing an adjacency list for each node, carrying out the traversal, obtaining a loop queue, carrying out the standardization processing, and removing repeated loops. All non-repeated standard loop queues are obtained; the standardization processing comprises the following steps: acquiring a unique identity identifier of each edge in a current loop queue; circularly shifting the edge corresponding to the unique identity label with the minimum value to the first position of the current loop queue to obtain a candidate loop queue; if the second element in the candidate loop queue is smaller than the last element, determining that the candidate loop queue is a standard loop queue after standardization processing; otherwise, all elements in the candidate loop queue are stored again according to a reverse sequence, then cyclic shift is executed, a standard loop queue is obtained, and all network loops can be rapidly detected.

The invention relates to the technical field of electronic design automation, and provides an intelligent three-dimensional design optimization system for an ink-jet circuit board. The system comprises a field programmable gate array core control module, a microcontroller co-processing module, a multi-channel stepping motor driving module, a multi-mode communication interface module, a sensor feedback and state monitoring module and a three-dimensional layout optimization structure. High-precision real-time control and management are realized through heterogeneous cooperation of the programmable gate array core control module and the microcontroller cooperative processing module; in cooperation with multi-channel stepping motor driving, multi-mode communication and sensor feedback, a three-dimensional layout optimization structure is used for carrying out system space optimization on components, signals and a power supply, and heat dissipation, electromagnetic compatibility and signal integrity are remarkably improved. According to the system, the control precision and the real-time monitoring and remote management efficiency are effectively improved, the response speed, the operation stability and the maintainability of the system are enhanced, and high integration level and high reliability are achieved.

The invention provides a logic synthesis optimization method and device, electronic equipment and a computer storage medium, and belongs to the technical field of EDA, and the logic synthesis optimization method comprises the steps: determining a target module included in an optimization strategy based on a time sequence report generated in a logic synthesis process; in the optimization strategy, a register retiming function and a register optimization function of the target module are enabled, so that the electronic design automation tool allows the registers between the modules to be moved when optimizing the target module; and based on the optimization strategy, executing logic synthesis on the to-be-synthesized design. A key bottleneck module influencing time sequence convergence can be optimized in a targeted manner in a logic synthesis process.

The present invention relates to a method of optimizing design (201) comprising the steps of obtaining at least one design (201) from at least one electronic design automation (EDA) tool (113); defining said design's at least one goal (205) and optimizing said design's at least one parameter (203) with at least one multi-agent design optimizer (107).

The invention relates to the field of artificial intelligence, natural language processing and electronic design automation, in particular to a circuit analysis generation and modification method based on form and logic separation, comprising the following steps: step 1, a complete circuit generation process; 2, separating and analyzing logic and form; step 3, intelligently modifying an operator; and step 4, labeling-generating-modifying a system: step 1, converting a natural language to a DSL code, then converting the DSL code into a logic diagram structure, and finally generating a morphological layout and a complete circuit diagram. According to the method, a complete process from a natural language to DSL, a logic diagram, morphological layout and a final circuit is achieved, the intelligent degree of circuit analysis is improved, through morphological and logic decoupling, the generalization ability of circuit analysis is improved, the complete automatic process from natural language description to final circuit generation is achieved, meanwhile, efficient circuit modification and optimization are supported, and the method is suitable for popularization and application. The method also provides a modification operator, supports accurate circuit adjustment, and improves the design efficiency.

The invention discloses a module schematic diagram automatic design method suitable for electronic product design, and belongs to the technical field of electronic design automation. The method aims at solving the problems that traditional manual schematic diagram design is low in efficiency, prone to errors and highly dependent on experience of engineers. The method comprises the following steps: firstly, carrying out structured information modeling on a design demand, a design template and a to-be-generated module; secondly, according to the design requirement after modeling, all candidate main chip sets meeting the conditions are screened out from a device library; then, aiming at each candidate main chip, automatically constructing a peripheral circuit of the candidate main chip through a template matching process; and finally, calculating the general device in the template according to the parameters of the main chip and replacing the general device with an actual device with a specific model. According to the method, various module schematic diagram schemes which conform to specifications and can be optimized can be quickly and accurately generated according to a single design requirement, the automation level and efficiency of electronic design are remarkably improved, and the design threshold is reduced.

The invention discloses a PCB layout evaluation method and system integrating layout optimization and resource evaluation, and a medium. Relates to the technical field of electronic design automation. The scheme is based on PCB layout design, layout resource evaluation and layout quality evaluation; according to the method, the devices on the PCB are arranged and placed in combination with the minimum area constraint of the distance constraint between different devices, meanwhile, the actual effective area on the PCB is analyzed and evaluated, the effective utilization degree of the PCB is reflected, an engineer is assisted in predicting the PCB layout design resource condition in advance, the utilization rate of the PCB is conveniently optimized, and the PCB layout design efficiency is improved. Therefore, the raw material cost and the manufacturing cost of the PCB are reduced; after the layout is completed, the layout is evaluated from the overall layout to the local layout, guidance is provided for optimization of the layout result, and the PCB layout design quality and reliability are improved.

The invention relates to the technical field of electronic design automation, and discloses a performance optimization method and system for an integrated circuit debugging tool, and the method comprises the steps: analyzing a design file, constructing an analysis database, carrying out the dynamic complexity evaluation of each module in the design based on a plurality of preset complexity indexes, and generating a module complexity classification result; according to the module complexity classification result, dividing the module into a complex module, a top-layer module and a lightweight module, and executing pre-refining processing on the complex module and the top-layer module to generate a core refining database; in the user interaction process, according to user operation behaviors, dynamically triggering refinement processing on an unloaded module, and supplementing a refinement result to the core refinement database as required; a user interface is updated in real time based on the core refinement database, a non-delay module hierarchical structure and signal information display are provided, tool initialization time and memory consumption are remarkably reduced, and large-scale circuit debugging efficiency is improved.

The invention provides a dynamic predictive job scheduling method, which comprises the following steps of: acquiring a configuration file of a to-be-scheduled EDA (Electronic Design Automation) task by a scheduling central system, and extracting job characteristics of the to-be-scheduled EDA task; acquiring real-time monitoring data of the current running task from the computing node cluster; the prediction engine predicts the to-be-scheduled EDA task and the current running task according to the job characteristics and the real-time monitoring data to obtain first prediction data of the to-be-scheduled EDA task and second prediction data of the current running task, and the first prediction data and the second prediction data are fed back to the scheduling center system; the scheduling center system sends the first prediction data, the second prediction data and the real-time monitoring data to a decision engine; the decision engine determines a resource preemption strategy of the to-be-scheduled EDA task and feeds back the resource preemption strategy to the scheduling center system; the scheduling center system determines the execution sequence of the EDA tasks to be scheduled and sends the execution sequence to an execution engine; and the execution engine performs resource allocation on the to-be-scheduled EDA task.

The invention relates to the technical field of electronic design automation design, in particular to a snapshot output method for effective paths in a network, electronic equipment and a storage medium, and the method comprises the steps: obtaining all effective paths in the current network, and obtaining an effective path set; in the process of acquiring the effective path, acquiring a node of which the role type is an end point; according to the effective path set and attribute information carried by nodes and edges in each effective path, a current network name is output, nodes and snapshot information thereof are output according to a node sequence in each effective path, and the snapshot information comprises a current node name, a role type, a node position and an accumulated path length of each node; the cumulative path length is the cumulative sum of all continuous routing and fly line lengths from the starting node of the effective path to which the current node belongs to the current node, the technical problem that the effective path in the network and related information of the nodes in the path cannot be effectively acquired at present is solved, and effective data is provided for simplifying simulation.

The invention relates to the technical field of electronic design automation and artificial intelligence, in particular to an AI-assisted multi-target PCB automatic design system and method, and the system comprises a user interface layer which is used for a user to input a request through a Web-based interface; the natural language analysis module is used for processing the request and generating a JSON (JavaScript Object Notation) containing function requirements; the device selection module queries an internal device database and suggests an ESP32-C3 MCU (Microprogrammed Control Unit), a compatible relay and a support circuit; the circuit generation module is used for creating a netlist and a schematic diagram file and comprises an MCU (Microprogrammed Control Unit), a relay driver and related passive elements; the layout optimization module runs a multi-target algorithm and is integrated with PCB design software; experimental verification shows that compared with a traditional one-way process, by means of the method, the requirement interpretation accuracy can be improved to 94.2% from 76.3%, the design intention preservation rate is improved to 89.5% from 42.7%, the requirement change adaptation time is shortened to 2.1 h from 8.4 h on average, and the requirement interpretation efficiency and accuracy are improved.

The invention discloses a BGA simultaneous escape wiring method based on shared node and combined congestion negotiation, and belongs to the technical field of electronic design automation. The method comprises the following steps: constructing a directed graph representing a wiring space, and determining a starting point and an ending point of each to-be-wired network; adopting a bidirectional Dijkstra algorithm to carry out parallel path search on all the networks; dividing the line network into a single line network and a conflict line network containing shared nodes; the conflicting networks are grouped, so that the networks in the group only share nodes with one another; on the basis of a network quality evaluation model, selecting one network from each group to remove the network, and dynamically updating the cost value of wiring nodes; and iteratively executing the steps of searching, grouping, clearing and cost adjustment until all the wire nets are single wire nets, and outputting a final wiring result. According to the method, wiring congestion can be effectively reduced, path bypassing is avoided, and the success rate, the wiring quality and the algorithm convergence efficiency of BGA packaging and escape wiring are remarkably improved.

The invention relates to the technical field of electronic design automation, in particular to a method for collecting flipping coverage rate data during simulation, electronic equipment and a storage medium, and the method comprises the steps: registering a value change callback function for each instantiated flipping variable; when the flip variable is the scalar variable, the monitoring object of the value change callback function is the scalar variable; when the flip variable is an aggregation variable, the monitoring object of the value change callback function is each sub-variable; during simulation, if the value of the monitoring object in the flip variable changes, collecting coverage state data of the target monitoring object through a value change callback function, and updating a target bit corresponding to the target monitoring object in the coverage state bits according to the coverage state data; and when all the coverage data of the coverage state bit are valid data, deleting the value change callback function registered for the target flip variable, thereby improving the simulation efficiency and the resource utilization rate.

The invention provides a multi-modal knowledge graph generation method and system for hardware design analysis, which break through design, verification and physics, realize information barriers among the three traditional EDA (Electronic Design Automation) fields, perform semantic fusion and association on information from different data fields, create a unified and queriable hardware design knowledge representation, and improve the reliability of hardware design analysis. And a coherent and operable unified knowledge model is formed. A multi-modal design knowledge graph is created by integrating a simulation result (dynamic data) and a physical implementation feature (performance data) into a static structure model, and a comprehensive design model with structure, behavior and performance features is analyzed in a unified framework. An engineer does not need to manually switch between different tools and data formats, but can access all-dimensional information about a static structure, a dynamic behavior and a physical property of a design through a single query interface.

The embodiment of the invention relates to an AI-based design optimization system and method. The system comprises an AI module, a processing analysis module, a DOE module, an EDA module and an optimization module. And the AI module is connected with the processing analysis module, the DOE module, the optimization module and the EDA calling module, and is used for receiving the design task, performing disassembly, distribution and process planning on the design task, and optimizing the process and parameters of the design task based on a preset AI model. According to the technical scheme provided by the embodiment of the invention, the AI tool represented by the large language model is fused into the parameter optimization process, and full-autonomous decision and control of links such as parameter control, optimization control, experimental design, data analysis and application in the whole optimization process are realized by utilizing experience knowledge and professional knowledge built in the large language AI model, so that the optimization efficiency is improved. And the optimization process from'task input 'to'task output' without human intervention in a real sense is realized.