The invention discloses verifying environment patterned chip verifying method and device, and relates to the field of electronic design automation (EDA) verification in a chip designing process. The method comprises the following steps: establishing a new test sample, grouping test points according to functions, automatically generating an input document required by chip verification in a patterning mode, and configuring parameters of a simulator; running the test sample, directly interacting with the simulator, and displaying encoding and simulating information of the simulator in a graph mode; observing the test result, verifying the next test sample if the test is successful; and performing regression testing after codes are modified if a fault sample is found. By utilizing the method,the patterning operation and management of chip verification can be realized, the time spent in studying new verification language by testing staff is saved, and the chip verification process becomessimple and intuitive, so that the studying cost of the testing staff is reduced, the chip verification period is greatly shortened, and the efficiency of chip verification is improved.