355 results about "Electronic design automation" patented technology

The invention relates to the technical field of electronic design automation, in particular to a local layout wiring method based on sequence value correction and historical guidance search, which comprises the following steps: calling a multi-source dynamic sequence value wave diffusion path search sub-algorithm, generating initial paths for all wire nets, and initializing a historical solution set and a current solution sequence; random disturbance is carried out based on the current solution sequence, and candidate solutions are generated; judging whether the candidate solutions meet design rule constraints or not; checking whether the maximum iteration frequency is reached or no improvement frequency limit exists, if yes, entering the step of outputting the optimal solution, and otherwise, returning to the step of generating the candidate solution; selecting a wiring path which has an optimal target function value and meets all constraints from the historical solution set, and outputting a final result; according to the local layout wiring method based on sequence value correction and historical guidance search, the problems of high-density region wiring feasibility, complex design rule satisfaction, multi-objective optimization, calculation efficiency and the like can be solved.

The invention belongs to the technical field of electronic design automation, and provides a dynamic power consumption optimization method, electronic equipment and a storage medium, and the method comprises the steps: obtaining a circuit design, and determining a starting point of a specific type in the circuit design; performing backward traversal on the circuit design along a signal propagation direction from the starting point to determine circuit branch structure information and a specific type of termination point in the circuit design; starting from the termination point, establishing an ODC expression, performing forward traversal on the circuit design in an inverse signal propagation direction, and in the forward traversal process, based on the circuit branch structure information, propagating the ODC expression in the circuit design until ODC distribution of the circuit design is determined; based on the ODC distribution, dynamic power consumption optimization is performed on the circuit design. According to the method, the ODC expression can be quickly and efficiently propagated in the whole circuit design, so that a designer can conveniently optimize the dynamic power consumption through ODC distribution.

The invention relates to a software and hardware SOC (System On Chip) verification system and method based on EDA (Electronic Design Automation) and an FPGA (Field Programmable Gate Array), and belongs to the field of SOC chip verification. The software part comprises an SOC UVM TESTBENCH SOC verification platform, a disk network disk and a T CP protocol client side; and the hardware part mainly comprises a TCP (Transmission Control Protocol) SERVER protocol server side and a SOCTOP (System On Chip Over Programmable). The method is characterized in that advantages of EDA verification and FPGA prototype verification are combined, cross-platform accelerated verification of the SOC chip is realized, the verification period of the chip is shortened, and the verification quality of the chip is improved.

The invention discloses a PCB component layout method, device and equipment based on a multi-modal large model, and relates to the technical field of electronic design automation, the method comprises the following steps: carrying out quality screening on a plurality of PCB design files which have been laid out to obtain a qualified design file set; constructing a serialized training sample set based on the qualified design file set; each training sample sequence comprises a plurality of training samples arranged according to a layout logic sequence; each training sample comprises multi-modal data representing a current layout state and a real position coordinate of a next component to be laid out; based on the serialized training sample set, training the open-source multi-modal large model to obtain a PCB component layout model; and iteratively generating a layout file of the target PCB based on the netlist file of the target PCB and the PCB component layout model. The method is high in generalization capability and low in cost based on the PCB component layout model trained by the layout data, and can realize rapid layout of components of a new PCB.

The invention discloses a PCBA (Printed Circuit Board Assembly) processing component layout optimization method and system, and relates to the technical field of electronic design automation. Data stream information of each functional module of a PCBA is collected, data stream characteristics are analyzed, and key signal paths and interaction relationships are determined; the method comprises the following steps of: dividing priorities for different data streams according to functional requirements and signal importance of a PCBA (Printed Circuit Board Assembly), and determining a core signal; by optimizing component layout, reducing roundabout and intersection of signal paths, reducing signal transmission loss and interference, reasonably dividing functional areas and compactly arranging associated components according to data stream directions and core signals, it is ensured that the signal transmission paths are clear and efficient, meanwhile, the transmission quality of high-priority signals is preferentially guaranteed, and the transmission efficiency is improved. By adopting a transmission line with strong anti-interference capability, adding a signal buffer and filter circuit and other measures, the signal integrity is obviously improved, and the signal is kept stable and reliable in the transmission process, so that the performance of the whole PCBA system is improved.

The invention discloses a PCB layout optimization method, system and device based on an evolutionary algorithm and a medium, and relates to the field of electronic design automation, and the method comprises the steps: S1, obtaining an initial layout generated by a PCB; s2, judging whether the number of iterations is greater than or equal to the maximum number of iterations; s3, if yes, ending; s4, if not, random disturbance is generated according to the current layout, and a new layout is generated; s5, comparing the new layout with the current layout by adopting an objective function, and judging whether the new layout is superior to the current layout or not; s6, if not, whether the acceptance probability function is larger than a set value or not is judged; s7, if not, returning to S2; s8, if the acceptance probability function is greater than a set value or the new layout is superior to the current layout, taking the new layout as the current layout; and S9, when the current layout is superior to the optimal layout, updating the optimal layout by using the current layout, and returning to S2. According to the method, optimization of the layout of the PCB is realized, and a more ideal layout effect is achieved.

The invention provides an electronic design automation simulation system-on-chip double-rate synchronous dynamic random access memory verification method and verification system, a test device and computing equipment, the method is applied to a startup program, and the method comprises the following steps: obtaining a test case designed according to the characteristics of a double-rate synchronous dynamic random access memory needing to be verified; running a first-stage boot loader; running a second-stage boot loader, and completing initialization of the double-rate synchronous dynamic random access memory; running a third-stage boot loader, loading the test cases in sequence, and carrying out electronic design automation simulation verification; and outputting a verification result through the central processing unit to complete the characteristic verification of the double-rate synchronous dynamic random access memory. According to the technical scheme of the invention, the complexity of DDR verification can be reduced, and high-efficiency DDR verification is realized.

Method and servers for determining optimized device parameters of an electronic circuit. The method includes accessing design information of the electronic circuit, determining a set of device parameters of the electronic circuit based on the design information, receiving information indicative of set of performances-of-interest to be optimized, and a corresponding set of target values, each target value being associated with a corresponding performance-of- interest, defining a multi-objective reward function based on the set of performances-of-interest to be optimized and outputting, using a pre-built Machine Learning (ML) algorithm interacting with an electronic design automation (EDA) environment, an optimized device parameter value for each of the device parameters based on the multi-objective reward function.

The invention relates to the technical field of electronic design automation, in particular to a coverage rate-based index database management method, coverage rate-based index database management equipment and a storage medium. Meanwhile, extracting design level information in the coverage rate database to establish an index database consisting of a plurality of index tables; when the visual query window initiates a query request, the index database queries the identifier of the target object according to the query request, and processes and updates the target window of the coverage rate visual system according to the identifier in the coverage rate data structure, so that the search efficiency is greatly improved, and the search time is shortened. And the purpose of real-time searching is achieved.

The invention belongs to the field of electronic design automation, and discloses a multi-agent radio frequency circuit netlist generation method and system based on a large language model, and the method comprises the steps: preparing a data set, and constructing a knowledge base; the method comprises the following steps: receiving and analyzing a natural language demand of a user, combining a cue word project and an RAG mechanism, carrying out chained reasoning, introducing a radio frequency design rule, and converting the information into structured parameter information; combining RAG knowledge base retrieval and new topology generation, and fusing PDK process constraints to obtain candidate topologies and a simulation netlist; a simulation tool is called to execute parameter analysis, iterative optimization is conducted on parameters in combination with a closed-loop feedback mechanism, and a final netlist meeting user requirements is obtained. Automatic decomposition, parallel cooperation and high-speed iteration of design tasks are achieved through multi-agent cooperation and in combination with the radio frequency knowledge graph and the RAG; introducing physical constraints to enable the generated topological structure and parameters to meet the physical constraints; and a closed-loop simulation feedback mechanism is fused, so that the dependence on manpower is reduced.

The invention belongs to the technical field of electronic design automation, and provides a waveform propagation method, electronic equipment and a storage medium, and the method comprises the steps: obtaining a circuit design and a waveform file; initial waveform information matched with the target design hierarchy of the circuit design is determined in the waveform file; establishing a binary decision diagram for each instance of the target design hierarchy, and packaging the established binary decision diagrams to a uniform interface to call the binary decision diagram of each instance through the uniform interface; and based on the initial waveform information, starting from a first instance in each instance, performing waveform propagation by using a uniform interface until complete waveform information of the target design hierarchy is obtained. Waveforms of all devices in the whole design can be quickly established in the early stage of integrated circuit design, and the problem that it is difficult for a designer to obtain post-simulation waveforms to accurately calculate circuit power consumption in the early stage is solved.

The invention relates to the technical field of electronic design automation, and discloses a standard cell layout legalization method and system based on a graph theory constraint graph, and the method comprises the steps: building a bidirectional directed constraint graph based on an existing layout and a design rule, and building a directed edge between adjacent graph edges according to the design rule; traversing the constraint graph, detecting whether a directed edge which does not meet a constraint condition exists, and if so, identifying the directed edge as a constraint violation edge; for two end points of each constraint violation edge, searching a key path based on a depth-first search algorithm, and determining a maximum movable distance in combination with a greedy strategy; moving the endpoint to a legal position according to the critical path and the maximum movable distance, and updating the position of a related node in the constraint graph; and mapping the position changes of the nodes in the constraint graph back to the corresponding graph edges in the layout, and outputting the legalized layout, so that efficient and automatic repair of design rule violation is realized through the method, and the layout compliance rate and the area optimization effect are remarkably improved.

A method for data center switching fabric path emulation in an electronics design automation (EDA) environment includes generating emulated data center traffic. The method further includes, at a path emulation element, modifying the emulated data center traffic to emulate passing of the emulated data center traffic through a data center switching fabric. The method further includes outputting, by the path emulation element, the modified emulated data center traffic to an EDA emulator emulating an electronics design under test. The method further includes receiving and storing a response of electronics design under test to the modified emulated data center traffic.

The invention relates to the technical field of electronic design automation, and provides a printed circuit board wiring method and device, equipment, a medium and a program, and the method comprises the steps: classifying an obstacle as a pushable object or a non-pushable object; based on the relative position relationship between the initial path and the pushing object, constructing a geometric occupied area of the pushing object, and performing path offset on the pushing object according to the geometric occupied area; in the deviation process, if the distance between any deviated object capable of being pushed and any deviated object not capable of being pushed is smaller than a preset safety distance, further deviation is stopped, and the deviated object capable of being pushed is reversely returned along the deviation track of the object until the distance between the object capable of being pushed and the object not capable of being pushed is larger than or equal to the safety distance; and re-planning a final path of the signal line according to the position of each pushable object after returning, and outputting a wiring result according with a wiring rule. The method is used for optimizing and completing signal path optimization and distribution in an environment with obstacles.

A method of designing a programming and / or emulation tool for a processor includes developing a single model of the processor from a group including: the processor; hardware description of the processor; and a specification of the processor that is confirmed to represent the processor and / or hardware description; and automatically generating, by the electronic design automation tool, a programming and / or simulation tool of the processor from the single model of the processor and the set of design parameters. The method also includes validating a programming and / or emulation tool of the processor using the one or more validation applications and the reference entity.

The invention provides a DFT process monitoring method and device, electronic equipment and a storage medium, and belongs to the technical field of DFTs. The DFT process monitoring method comprises the steps that in response to monitoring that execution of a current test task is finished, a process state and a current log file generated in the process of executing the current test task are obtained; determining a target predefined analysis rule corresponding to the type of the EDA tool adopted for executing the current test task through a mapping relation between the type of the EDA tool and the predefined analysis rule; analyzing the current log file through a target predefined analysis rule to obtain semantic keywords; and determining a final execution state of the current test task based on the process state and the semantic keyword. According to the scheme, massive unstructured log files generated by different EDA tools can be analyzed, and the final execution state of each test task can be determined.

The invention relates to a unified PDK interface specification-based conversion method, and relates to the technical field of electronic design automation, and the method comprises the following steps: obtaining commercial PDK data; performing semantic analysis and structure reconstruction on the model file based on a machine learning transfer learning algorithm to generate a standardized intermediate model; according to a unified PDK interface specification, converting the intermediate model into target PDK data conforming to an independent research and development simulation platform format; and automatically importing the target PDK data to the simulation platform through the templated script, and verifying the integrity and consistency of the target PDK data. The method can be applied to a core particle system design process, unified access and co-simulation of the commercial PDK and the open-source PDK are realized, and the design efficiency of an integrated circuit is improved.

The invention relates to a defect analysis and process optimization method based on artificial intelligence multi-mode fusion, and the method comprises the steps: respectively inputting virtual data of a chip or device design layout, an expected process flow and parameters, and an expected electrical performance curve into an image encoder, a process encoder, and an electrical encoder, extracting a corresponding feature vector; performing cross-modal information interaction on the corresponding feature vectors according to a cross attention fusion mechanism; determining a representation image, a defect category, a root cause category and a process parameter correction suggestion; and based on a manufacturing execution system (MES), an electronic design automation (EDA) tool or an equipment interface, process parameters are corrected, and a closed-loop control result from defect analysis to process optimization is obtained. Therefore, the problems of single data dimension, mutual coupling of various defects, influence of background noise, limited machine identification accuracy, overlarge workload of artificial expert judgment and low efficiency are solved.

The invention discloses a circuit netlist conversion method, a circuit netlist conversion control method and a circuit netlist conversion control device. The method comprises the steps that a circuit netlist is obtained and analyzed, netlist intermediate data are constructed, the netlist intermediate data comprise netlist element data and netlist topological data, the netlist element data are used for representing electrical parameters of circuit elements, and the netlist topological data are used for representing the connection relation of the circuit elements; converting the netlist element data into schematic diagram element data according to an element configuration rule of the target electronic design automation tool; determining position information of the circuit elements and routing information between the circuit elements based on the netlist topological data, and generating schematic diagram layout data adaptive to the target electronic design automation tool; and according to the schematic diagram element data and the schematic diagram layout data, generating a circuit schematic diagram file through the target electronic design automation tool. The circuit netlist conversion method has the technical effect of improving the circuit netlist conversion efficiency.

The invention provides a DFT resource configuration prediction method and device, electronic equipment and a storage medium, and belongs to the technical field of electronic design automation, and the method comprises the steps: determining a reference device density based on a process node of a target chip; determining an effective digital logic layout area based on the chip planning area of the target chip and the estimated non-digital logic function region; according to a utilization rate factor corresponding to the physical design constraint of the target chip, correcting the effective digital logic layout area to obtain an available standard cell layout capacity; according to the standard unit layout capacity and the reference device density, generating a time sequence element number prediction interval of the target chip through a logic depth mapping model; and according to the time sequence element number prediction interval, generating testability design DFT architecture configuration parameters of the target chip. The number of chip registers can be quickly and accurately predicted and the DFT architecture configuration parameters can be generated in the early stage of chip design.

The invention relates to the field of electronic design automation, provides a method for semi-automatically processing an EDA (Electronic Design Automation) project file and generating a YOLO format annotation data set, and aims to solve the technical problems of low efficiency and poor precision of the traditional pure manual data annotation data set. According to the main scheme, the method comprises the steps of reading an engineering file of a jia-creative EDA project, analyzing and extracting element information, generating a standardized CSV data format, converting the standardized CSV data format into a label in a YOLO format, calculating normalized bounding box coordinates of elements, and recognizing special original elements and supplementing labeling information in combination with a template matching technology; drawing a bounding box on the schematic diagram image according to a YOLO label, highlighting different element types by using different colors, and generating a visual annotation image; revising and combining the newly generated YOLO label and a preliminary YOLO label generated by the AI model to obtain a label set; then importing into Labelimg for manual correction, and generating a final label set; and training a target detection model by using the final label set, and improving the pre-labeling precision through data set expansion iteration.

The invention belongs to the field of electronic design automation (EDA), and particularly provides a logic comprehensive optimization operator acceleration method, which introduces a screening strategy of a sub-circuit diagram, and improves the optimization efficiency of an operator on the premise of ensuring the optimization quality of the operator. According to the method, the sub-circuit diagrams are classified by using the graph neural network, and the sub-diagrams suitable for operator execution are screened out, so that all the sub-diagrams are prevented from being traversed, and the operator execution speed is increased; in the sub-graph screening, a screening range is set according to the execution sequence of operators, a relatively large screening range is set for the operators executed firstly so as to obtain a better optimization effect, and a relatively small screening range is set for the operators executed later so as to obtain a higher execution speed; in conclusion, the characteristic that the logic comprehensive optimization operator is continuously executed in a sequence mode is utilized, and the operator optimization efficiency is improved on the premise that the operator optimization quality is guaranteed.

The embodiment of the invention provides a packaging file generation method and device, electronic equipment and a storage medium. The method comprises the steps that a first packaging file expressed in a first packaging format is obtained; reading packaging information of the component from the first packaging file; determining a to-be-converted packaging element of the component based on the packaging information; target electronic design automation software and a second packaging format for the target electronic design automation software are determined; converting the to-be-converted packaging element into a target element expressed in the second packaging format; and the second packaging file for the target electronic design automation software is constructed by adopting the target element, so that the packaging formats of different EDA software are converted, the tedious work of manually recreating or editing the packaging information is avoided, and the design efficiency is improved.

The invention relates to the technical field of electronic design automation, in particular to a function coverage rate data compression and storage method, system and device and a storage medium. Collecting the coverage rate of each coverage point or cross coverage and the hit times of each bin subordinate to the coverage point or the cross coverage; acquiring a coverage rate grade and a corresponding data structure; dynamically selecting a target data structure according to the target coverage rate grade of the coverage rate of the target coverage point or the cross coverage; operating a corresponding target data structure through a dynamic storage selector according to the target data structure, wherein the target data structure comprises a flag bit of the current data structure and storage structure data; wherein the storage structure data comprises at least one of the serial number of the bin and the hit frequency of the bin, and the storage overhead is remarkably reduced.

The invention relates to the technical field of electronic design automation, in particular to a network loop detection method based on deep traversal, electronic equipment and a storage medium, and the method comprises the steps: obtaining a node set and an edge set under a target network, constructing an adjacency list for each node, carrying out the traversal, obtaining a loop queue, carrying out the standardization processing, and removing repeated loops. All non-repeated standard loop queues are obtained; the standardization processing comprises the following steps: acquiring a unique identity identifier of each edge in a current loop queue; circularly shifting the edge corresponding to the unique identity label with the minimum value to the first position of the current loop queue to obtain a candidate loop queue; if the second element in the candidate loop queue is smaller than the last element, determining that the candidate loop queue is a standard loop queue after standardization processing; otherwise, all elements in the candidate loop queue are stored again according to a reverse sequence, then cyclic shift is executed, a standard loop queue is obtained, and all network loops can be rapidly detected.

The invention relates to an electronic product PCB design system and method. In the system, a data preparation and knowledge base construction module is used for collecting, cleaning and de-duplicating multi-source PCB design data and constructing a comprehensive PCB design knowledge base; the polymorphic large model construction and training module adopts a hybrid neural network based on a transformer architecture, and constructs a polymorphic large model with a cross-modal reasoning capability by jointly training a schematic diagram semantic understanding model, a layout topology optimization model and a signal integrity prediction model; the intelligent auxiliary Agent module is used for integrating a reinforcement learning agent and a rule verification agent, and providing a wiring path optimization suggestion, element type selection recommendation and design specification compliance detection in real time; and the system integration module is used for automatically designing the generation module and converting the optimization scheme output by the polymorphic large model into a final PCB design file. The system can improve the design automation level.

The invention provides a storage and calculation fusion architecture parameter configuration method for a neural network model, and is applied to the technical field of electronic design automation and integrated circuits. Comprising the steps that pruning is conducted on a first feature space according to a feature importance vector of the storage and calculation fusion architecture, a second feature space is obtained, and a plurality of elements included in the feature importance vector are used for representing relative importance of a plurality of hardware parameters of the storage and calculation fusion architecture; determining a plurality of first features in the second feature space, wherein the first features comprise parameter values of the hardware parameters; for each first feature, according to the first feature and the model parameter feature of the neural network model, predicting the operation performance of the neural network model on the storage and calculation fusion architecture to obtain a first performance value corresponding to each first feature; determining a target feature in the plurality of first features according to the plurality of first performance values; and performing parameter configuration on the storage and calculation fusion architecture according to the parameter value of each hardware parameter included in the target feature.

The invention relates to the technical field of electronic design automation, and provides an intelligent three-dimensional design optimization system for an ink-jet circuit board. The system comprises a field programmable gate array core control module, a microcontroller co-processing module, a multi-channel stepping motor driving module, a multi-mode communication interface module, a sensor feedback and state monitoring module and a three-dimensional layout optimization structure. High-precision real-time control and management are realized through heterogeneous cooperation of the programmable gate array core control module and the microcontroller cooperative processing module; in cooperation with multi-channel stepping motor driving, multi-mode communication and sensor feedback, a three-dimensional layout optimization structure is used for carrying out system space optimization on components, signals and a power supply, and heat dissipation, electromagnetic compatibility and signal integrity are remarkably improved. According to the system, the control precision and the real-time monitoring and remote management efficiency are effectively improved, the response speed, the operation stability and the maintainability of the system are enhanced, and high integration level and high reliability are achieved.

The invention relates to the technical field of electronic design automation, in particular to a concurrent clock optimization and data optimization method and tool, computer equipment, a medium and a program. The concurrent clock optimization and data optimization method comprises the following steps: providing a clock optimizer, and constructing a clock tree; initial skew on the clock tree is obtained, and the clock optimizer carries out balance processing on the clock tree based on the initial skew, so that the clock tree obtains useful skew; integrating the clock optimizer and the data optimizer to obtain a concurrent optimizer; and simultaneously performing data optimization on the balanced clock tree by using a concurrent optimizer, and performing clock optimization on the balanced clock tree based on the useful skew. The problem that an existing optimization tool is poor in clock tree optimization efficiency is solved.

The invention provides a logic synthesis optimization method and device, electronic equipment and a computer storage medium, and belongs to the technical field of EDA, and the logic synthesis optimization method comprises the steps: determining a target module included in an optimization strategy based on a time sequence report generated in a logic synthesis process; in the optimization strategy, a register retiming function and a register optimization function of the target module are enabled, so that the electronic design automation tool allows the registers between the modules to be moved when optimizing the target module; and based on the optimization strategy, executing logic synthesis on the to-be-synthesized design. A key bottleneck module influencing time sequence convergence can be optimized in a targeted manner in a logic synthesis process.