Variability-Aware Asynchronous Scheme for High-Performance Delay Matching

Abstract

A system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description. Included in the automated transformation are techniques for synthesizing a variability-aware controller using a two-phase protocol, techniques for synthesizing a variability-aware controller using gated clocks and testability circuits, techniques for synthesizing a variability-aware controller optimized for performance, techniques for initializing the synthesized controller, techniques for dynamically minimizing power requirements, and techniques for interfacing the desynchronized circuit with external synchronous circuits. Also disclosed are techniques for implementing a system for automatically transforming a synchronous circuit description into an equivalent and provably correct desynchronized circuit description within the context of an electronic design automation design flow. Exemplary circuits used in the application of the aforementioned techniques are provided. Application of mathematical models and techniques used for proving equivalence between the input description and the resulting desynchronized circuit are presented and explained.

Description

CLAIM OF PRIORITY[0001]The present application for patent claims priority to Provisional Application No. 60 / 985,878 entitled “A Variability-Aware Asynchronous Scheme Based on Two-Phase Protocols and Delay Matching” filed Nov. 6, 2007, and assigned to the assignee hereof and hereby expressly incorporated by reference herein.FIELD OF THE INVENTION[0002]The present invention relates to asynchronous logic circuits and more particularly to automated synthesis thereof.BACKGROUND OF THE INVENTION[0003]A digital circuit is composed of two types of components: combinational and sequential. As shown in FIG. 1A the combinational components 1A10, 1A20, 1A30, and 1A40 implement Boolean functions, whereas the sequential components 1A50, 1A60, 1A70, and 1A80 act as memory elements that store the state of the circuit. The sequential components are usually implemented with flip-flops 1A50, or latches 1A60, and 1A70, or sometimes combinations of latches 1A80 in a master / slave arrangement. Most digita...

AI Technical Summary

Problems solved by technology

For these reasons, designers are conservative in their design of synchronous circuits and, in the actual circuitry, the clock often runs at a frequency slower than the one it could run at if it could dynamically adapt to any combination of process variations, data variations, and changing environmental operating conditions.

The elasticity in the data transmission requires extra storage to implement those registers that receive new incoming data but have not been able to deliver the previously stored data.

In a conventional synchronous design, it is not possible to store different data at each latch.

However, none of the previous proposals disclosed techniques adequate for a provably correct and fully automated flow covering any possible synchronous circuit.

Moreover, prior proposals included assumptions or limitations for desynchronization techniques that motivate the present disclosure.

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