13 results about "Full custom" patented technology

An improved cable management system used in connection with electronic equipment and devices which allows for wires and cables to pass through the vent and prevent dust ingress. The improved cable management system is comprised of a foam baffle which is fully customizable to fit into nearly any type of electronic enclosure and is rated UL94 (V0 or HF-1) per UL flammability standards.

The invention provides an SOC chip and electronic equipment, the SOC chip provided by the invention comprises a plurality of storage components, and each storage component comprises a physical layer module, a storage control module connected with the physical layer module and a storage module; the storage control module is used for transmitting a read-write operation instruction to the physical layer module, and the physical layer module is used for performing protocol processing on the read-write operation instruction to obtain a read-write control instruction and transmitting the read-write control instruction to the storage module so as to perform read-write control on the storage module; the physical layer module and the storage module are prepared through a full-custom process, and the time sequence parameter corresponding to the physical layer module is determined based on the time sequence parameter of the storage module in the full-custom process preparation. The physical layer module and the storage module are both prepared through a full-customization process, and the physical layer module can adjust the time sequence parameter corresponding to the physical layer module according to the time sequence parameter of the storage module during preparation, so that the physical layer module and the storage module can perform simulation at the same time, and the time sequence accuracy and the product reliability are improved.

We combine an array of waveguides having different lengths with a reconfigurable integrated optical network that allows full customization of the filter function after fabrication to provide optical filters. This customization can also optimize filter performance, compensating for fabrication errors or imprecision. This network can also self-configure automatically to the problem. Hence this approach provides a new class of compact, convenient, high-performance and highly customizable optical filters that are also suitable for mass manufacture on integrated photonics platforms.

A semiconductor die includes manually designed full-custom logic circuits implemented at transistor level and performing digital computation without use of standard-cell libraries or automated synthesis. The die lacks bond pads, wire-bond terminals, or through-silicon vias and operates only when bonded to another die or carrier through dense hybrid-bonded or microbump conductive interconnects. In related embodiments, a system includes such a compute die and a peripheral die providing power, clock, and communication functions. The architecture enables pad-less full-custom compute dies operating solely through inter-die bonding for all external connectivity.

A multi-die semiconductor assembly integrates a manually-designed full-custom compute die with a peripheral die providing input / output, memory, power, and clock resources through a hybrid-bonded electrical connection comprising chip-to-chip, chip-to-wafer, or wafer-to-wafer bonding. The compute die operates without bond pads, standard-cell libraries, or automated synthesis, and the assembly functions independently of qualified digital or analog intellectual-property resources for the compute-die process node. Dense hybrid-bonded conductive paths carry both signal and power, enabling early functional hardware at advanced nodes before design-library availability while sustaining high activation bandwidth for transformer-class inference workloads.

A semiconductor package includes a number of different substrate sections. Each substrate section includes one or more electronic components. Additionally, each substrate section is mechanically and electrically coupled together using various conductive columns and conductive apertures. Because the substrate sections are interconnectable, a shape and / or a size of the semiconductor package is fully customizable. Additionally, a layout of the various electronic components of the semiconductor package is also fully customizable.

This invention discloses a low-power FFT chip for real-time spectrum analysis of electroencephalogram (EEG) signals and its usage method. The chip includes an analog front-end module, a digital processing module, an interface and control module, and a low-power management and clock control module. The analog front-end module amplifies, filters, performs power frequency notch filtering, and performs analog-to-digital conversion on the input microvolt-level analog EEG signals. This invention integrates a low-noise analog front-end, a dedicated digital processing module, and a fine-grained power management module into a single chip, constructing a dual anti-interference link that combines analog and digital processing. While ensuring signal purity, the digital processing module accelerates real-time processing speed, and the overall power consumption is controlled through fully custom circuitry and dynamic power management. This solves the three major problems of poor real-time performance, high power consumption, and weak noise immunity in general-purpose processor solutions for EEG spectrum analysis, thus meeting the demanding requirements of wearable devices.

A dual-motor mixed-hybrid powertrain system, by performing digital pulse control (DPC) on the instantaneous power time-varying functions of an engine and a battery pack, can convert the complex surface-working-condition of an analog-electronic-control (AEC) engine in the existing technology into a simpler pre-defined line-working-condition of a DPC engine, multiplexing in time either a pre-defined high-state line-working-condition in the combustion high-efficiency zone or a pre-defined non-combustion low-state line-working-condition with zero fuel consumption and zero pollutant emissions, achieving decoupling between a DPC engine working condition and the overall vehicle working condition and decoupling between software and hardware of a hybrid powertrain. By software defining and over-the-air updating, the vehicle power management strategy can be customized quickly for each vehicle or transport event, to achieve online energy-saving and emission-reduction simultaneous global optimization under the premise of industry leading vehicle power and braking performance and full customization of a thousand vehicle and a thousand face.

The invention belongs to the technical field of integrated circuit core particle design and manufacturing, and particularly relates to a wafer level chip design and manufacturing collaborative acceleration method. The method comprises the following steps: analyzing customization requirements of an electronic circuit integration system, and determining core parameters of a radio frequency core particle and a power supply core particle; prefabricating two types of core particle bottom layer structures, customizing a top layer function layer, and constructing a multi-voltage domain power supply unit; and customizing wafer cutting specifications and bonding pad parameters, and adapting to direct lead bonding interconnection between the core particles. Through the innovation of prefabricating and customizing the collaborative architecture and the like, the problems that an existing full-customization mode is long in period and high in cost are solved, and rapid customization and efficient integration of the core particles are achieved.

A semiconductor device includes more than one billion functional transistors manually designed at the transistor level without use of standard-cell libraries, automated synthesis, or automated placement tools. The device may form a compute die performing digital arithmetic operations, optionally connected to a peripheral die through hybrid or microbump bonding. The architecture achieves transistor densities exceeding 200 million per square millimeter and functional operation independent of conventional digital-design flows, providing manufacturable high-performance compute hardware when automated design resources are unavailable.

A semiconductor system integrates a manually designed full-custom compute die implemented at transistor level without automated synthesis with an automatically synthesized logic die implemented using standard-cell libraries and automated tools. The dies, fabricated on different process nodes, are bonded through dense conductive interconnects to function as a unified device. Power, timing, and data are exchanged between the dies, allowing early high-performance compute architectures to be realized before automated tool enablement on advanced nodes.

An improved cable management system used in connection with electronic equipment and devices which allows for wires and cables to pass through the vent and prevent dust ingress. The improved cable management system is comprised of a foam baffle which is fully customizable to fit into nearly any type of electronic enclosure and is rated UL94 (V0 or HF-1) per UL flammability standards.

This invention discloses a cascaded single-bit SPI slave module, a serial-to-parallel conversion system, and its design method. The system consists of N cascaded single-bit SPI slave modules connected in sequence. Each module includes three flip-flops and three delay buffers, implemented through a transistor-level full-custom design. The module employs a dual-phase clock mechanism: at CLK... I Signal rising edge sampling D I Data is sent to internal nodes, and after being delayed by buffer T1 on the falling edge, it is output to D. O In CS I The rising edge of the signal outputs the internal data to the Q port. Buffers T2 and T3 are respectively connected to CLK. I CS I CLK is generated after signal delay. O CS O The output aligns the rising edges of the clock and control signals of the next-level module with the data valid window. This invention constructs an N-bit parallel output interface through modular cascading, eliminating the need for a complex clock tree network. It offers advantages such as small chip area, high operating speed, strong scalability, and convenient process migration, making it suitable for the initialization and configuration of high-speed digital-to-analog integrated circuits.