Asynchronous static random access memory based on internet protocol (IP) of synchronous static random access memory

Abstract

The invention provides an asynchronous static random access memory based on an internet protocol (IP) of a synchronous static random access memory, and the asynchronous static random access memory based on the IP of the synchronous static random access memory is formed by an asynchronous control circuit and a plurality of synchronous static random access memories. Internal clocking signals of the asynchronous control circuit are triggered for the plurality of synchronous static random access memories. The asynchronous control circuit is also responsible for buffering an address and other signals and sending the address and other signals to the selected synchronous static random access memory. Due to the fact that the IP of the synchronous static random access memory is one of the most basic IPs of an integrated circuit process line, the asynchronous static random access memory based on the IP of the synchronous static random access memory just needs to add an asynchronous control circuit to the complete an asynchronous static random access memory based on the IP of the mature synchronous static random access memory, and has the advantage of being short in design cycle, compared with a traditional full custom design process and method.

Description

【Technical field】 [0001] The invention relates to the technical field of static random access memory, in particular to an asynchronous static random access memory. 【Background technique】 [0002] Static random access memory (SRAM) is a common random access memory widely used in the field of integrated circuits. According to different interfaces, it is divided into synchronous SRAM and asynchronous SRAM. Among them, the synchronous SRAM IP (IP: Intelligent Property) applicable to the integrated circuit system on chip (SoC: System on Chip) is currently the most widely used, and has become one of the most basic IPs in the integrated circuit process line. Each mature Synchronous SRAM IP has been verified by large-scale mass production tape-out, has high reliability, and can provide necessary design data including detailed layout, netlist and timing information. [0003] Asynchronous SRAM does not have an input clock signal, and can only trigger corresponding operations by dete...

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Problems solved by technology

In the entire design process, on the one hand, it takes a lot of manpower and time to complete the circuit and layout design of each structure mentioned above; The whole design faces a relatively large design risk, and often needs to waste a lot of money and time for multiple tape-outs to meet the design requirements

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