Asynchronous static random access memory based on internet protocol (IP) of synchronous static random access memory

A static random and memory technology, applied in the direction of static memory, digital memory information, information storage, etc., can solve the problems of large waste, a large amount of manpower, and large design risks, and achieve high reliability, shorten the design cycle, and reduce design risks. Effect

Active Publication Date: 2013-04-24
XI AN UNIIC SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the entire design process, on the one hand, it takes a lot of manpower and time to complete the circuit and layout design of each structure mentioned abo...

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  • Asynchronous static random access memory based on internet protocol (IP) of synchronous static random access memory
  • Asynchronous static random access memory based on internet protocol (IP) of synchronous static random access memory
  • Asynchronous static random access memory based on internet protocol (IP) of synchronous static random access memory

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Embodiment Construction

[0040] Embodiments of the present invention will be further described below in conjunction with the accompanying drawings.

[0041] see figure 1 as shown, figure 1 It is an example of an asynchronous static random access memory based on a synchronous static random access memory IP implemented according to the present invention. An asynchronous static random access memory based on the synchronous static random access memory IP of the present invention includes an asynchronous control circuit S0 and at least one synchronous static random access memory IP connected to the asynchronous control circuit S0. This embodiment includes a synchronous static random access memory IP0 and a synchronous static random access memory. RAM IP1. The input of the asynchronous control circuit S0 is an asynchronous signal, and the output includes an internal clock signal CLK_async for triggering the operation of the synchronous SRAM IP. The input of the asynchronous control circuit S0 is ad...

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PUM

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Abstract

The invention provides an asynchronous static random access memory based on an internet protocol (IP) of a synchronous static random access memory, and the asynchronous static random access memory based on the IP of the synchronous static random access memory is formed by an asynchronous control circuit and a plurality of synchronous static random access memories. Internal clocking signals of the asynchronous control circuit are triggered for the plurality of synchronous static random access memories. The asynchronous control circuit is also responsible for buffering an address and other signals and sending the address and other signals to the selected synchronous static random access memory. Due to the fact that the IP of the synchronous static random access memory is one of the most basic IPs of an integrated circuit process line, the asynchronous static random access memory based on the IP of the synchronous static random access memory just needs to add an asynchronous control circuit to the complete an asynchronous static random access memory based on the IP of the mature synchronous static random access memory, and has the advantage of being short in design cycle, compared with a traditional full custom design process and method.

Description

【Technical field】 [0001] The invention relates to the technical field of static random access memory, in particular to an asynchronous static random access memory. 【Background technique】 [0002] Static random access memory (SRAM) is a common random access memory widely used in the field of integrated circuits. According to different interfaces, it is divided into synchronous SRAM and asynchronous SRAM. Among them, the synchronous SRAM IP (IP: Intelligent Property) applicable to the integrated circuit system on chip (SoC: System on Chip) is currently the most widely used, and has become one of the most basic IPs in the integrated circuit process line. Each mature Synchronous SRAM IP has been verified by large-scale mass production tape-out, has high reliability, and can provide necessary design data including detailed layout, netlist and timing information. [0003] Asynchronous SRAM does not have an input clock signal, and can only trigger corresponding operations by dete...

Claims

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Application Information

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IPC IPC(8): G11C8/04G11C11/413
Inventor 拜福君
Owner XI AN UNIIC SEMICON CO LTD
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