Master-slave follower type single-edge K value trigger constructing method utilizing circuit three-element theory and master-slave follower type single-edge K value trigger circuit

Abstract

The invention discloses a master-slave follower type single-edge K value trigger constructing method utilizing the circuit three-element theory and a master-slave follower type single-edge K value trigger circuit. The master-slave follower type single-edge K value trigger composed of a digital follower and an analog follower is obtained by means of the circuit three-element theory, a distinctive three-beat work mode is adopted, clock falling edge triggering is adopted, an identical simplest element level circuit structure is obtained under eight optimum coding, due to the fact that a slave follower is an NMOS tube source electrode follower, only the structure scale of a main follower becomes large along with the increase of the K value which is equal to 4,5,6..., other circuit structures do not change, the main follower is the digital follower composed of a high-pass variable-threshold PMOS tube, the output logic level clamp function is realized, and the anti-jamming capability is high. The master-slave follower type single-edge K value trigger circuit is simple in structure, can serve as a K value static storage cell of a K value SSRAM, and can be used in the VLSI field such as FPGA, CPLD, semi-custom or full-custom ASIC and storer and other digital IC technical fields.

Description

(1) Technical field [0001] The invention belongs to the field of digital integrated circuits, in particular to a construction method and a circuit of a master-slave follower type single-edge K-value flip-flop using the theory of three elements of a circuit. (2) Background technology [0002] With the rapid development of MOS integrated circuit technology, the integration scale is getting larger and the integration level is getting higher and higher, and VLSI (Very Large Scale Integrated Circuit) has some deficiencies: ① First, on the VLSI substrate, the wiring occupies more than 70℅ of silicon A large number of programmable internal wirings are also required in programmable logic devices to connect various logic function blocks or input / output to complete circuits with specific functions, and wiring (including programming connection switches) occupies a large part of the material. cost. It is very important to reduce the proportion of wiring cost. ②From the perspective of ...

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Problems solved by technology

[0002] With the rapid development of MOS integrated circuit technology, the scale of integration is getting larger and higher, and VLSI (Very Large Scale Integration) has some shortcomings: ① First, on the VLSI substrate, the wiring takes up more than 70℅ of silicon In programmable logic devices, a large number of programmable internal wiring is also required to connect each logic function block or input/output to complete a circuit with a specific function. Wiring (including programming connection switches) accounts for a large part of the material. cost

[0005] 1. In the realization of multi-valued circuits (K≥3), the existing semiconductor manufacturing process control MOS transistor threshold technology has great disadvantages: ① the range of control threshold is limited (because the ion implantation concentration is limited), and the control threshold in the process The amplitude often changes the performance of the MOS tube, and the voltage-type multi-valued circuit thus realized is not larger than the 4-valued circuit, and the application of more-valued circuits is difficult

② Only the amplitude of the threshold can be controlled, and the opening properties of the MOS tube cannot be changed (such as high-pass, low-pass, band-pass, and band-resistance). The simplest circuit structure

③ It is necessary to add an additional process of ion implantation, and the threshold can only be controlled in the semiconductor manufacturing process, which not only increases the complexity of the process, but also cannot be controlled by the user

[0006] 2. In the realization of multi-valued circuits, the existing neuron MOS transistor control threshold technology has great disadvantages: ① With the increase of K value, 'the input gate and control gate capacitance of a single neuron MOS transistor occupies the area of ​​the silicon chip' versus 'a single neuron MOS transistor'. The ratio of the MOS tube to the area of ​​the silicon chip is getting larger and larger, such as ten times, a hundred times or higher; ②As the K value increases, the width of th

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