Method of structuring multiport asynchronous storage module

A storage module and multi-port technology, which is applied in the field of building multi-port asynchronous storage modules, can solve problems such as bottleneck blockage, inability to meet the use requirements of asynchronous multi-single-port memories, and sacrifice design performance to achieve the effect of improving flexibility

Active Publication Date: 2013-02-13
NO 54 INST OF CHINA ELECTRONICS SCI & TECH GRP
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Problems solved by technology

If there is no storage module that supports high-speed parallelism in the circuit, it will easily cause bottleneck congestion during data exchange, thus affecting the data processing capability of the entire system
In integrated circuit design, because only simple single-port o...

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  • Method of structuring multiport asynchronous storage module
  • Method of structuring multiport asynchronous storage module
  • Method of structuring multiport asynchronous storage module

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Embodiment Construction

[0026] refer to Figure 1 to Figure 3 , a method for building a multi-port asynchronous storage module is characterized in that it comprises steps:

[0027] ① When performing a write operation, multiple write addresses enter the write address decoding module 100 , and multiple write data corresponding to the write addresses enter the write data decoding module 200 .

[0028] ②The write address decoding module 100 sends the multiple write addresses to the corresponding general-purpose memory in the memory bank 600 respectively, and simultaneously the write address decoding module 100 outputs the write operation identification to the flag bit control module 500; the write data decoding module 200 sends The multi-channel write data is respectively stored in the general-purpose memory corresponding to its write address, and the storage process of the write data is completed.

[0029] Wherein, in the ② step, the write address decoding module 100 sends the multiple write addresses ...

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Abstract

The invention discloses a method of structuring a multiport asynchronous storage module and relates to buffer storage and interchange of multichannel parallel data in the process of data interchange and processing. The method of structuring the multiport asynchronous storage module aims at solving the problem that in the process of design of a current semi-custom integrated circuit, a used storer of a technological library just has two types of single ports or double ports and can not meet certain situations of high data throughput rates. An addressing manner of address decoding control partitioning reading and writing is adopted by a plurality of double-port type storers in the technological library to structure the multiport asynchronous storage module, so that the aim that a simple port storage module is structured to the multiport storage module is achieved, and the requirement for the high data throughput rates is reached. The method of structuring the multiport asynchronous storage module has the advantages of flexibly expanding capacity and available access ports of the storer according to design requirements, reducing design difficulty, and shortening development time. Relative to a full-custom multiport storer, the method of structuring the multiport asynchronous storage module has the advantages of being good in flexible performance, high in reliability, small in design risk and the like.

Description

technical field [0001] The invention relates to a method for constructing a multi-port asynchronous storage module in integrated circuit design, which is especially suitable for high data throughput data exchange and data processing applications, and realizes storage and access control of multi-channel data. Background technique [0002] In high-speed parallel data exchange and processing systems, with the increase of data exchange volume and information processing tasks, the requirements for data transmission are getting higher and higher. If there is no storage module that supports high-speed parallelism in the circuit, it will easily cause bottleneck congestion during data exchange, thereby affecting the data processing capability of the entire system. In integrated circuit design, because only simple single-port or dual-port memory is provided in the process library, it cannot meet the designer's demand for asynchronous multi-single-port memory. The general solution is t...

Claims

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Application Information

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IPC IPC(8): G11C16/06
Inventor 田素雷刘淑涛张维周永川
Owner NO 54 INST OF CHINA ELECTRONICS SCI & TECH GRP
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