80 results about "Expanded memory" patented technology

A memory structure includes randomly accessible, channel-all-around ferroelectric memory transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film ferroelectric memory transistors. The three-dimensional memory stacks are manufactured in a process that includes forming holes in a multi-layer film stack for forming local word line structures and slit trenches to divide the film stack into memory stacks including local word line structures formed therein. The memory structure of channel-all-around ferroelectric memory transistors enables a scalable construction for realizing a high density, high capacity memory device.

Embodiments of this application relate to a server and an electronic device. The server and the device are used to resolve the problem that memory module groups inside a server are difficult to expand and therefore the processing performance of the server is limited. The server includes a mainboard, a CPU, and an expanded memory module group. The mainboard comprises memory expansion connectors. The CPU is on the mainboard and is coupled to the memory expansion connectors. The expanded memory module group is on one side of and spaced from the mainboard, and is coupled to memory expansion connectors.

A heat sink for a solid-state drive (SSD) storage device for use as an extended memory in an expansion slot of a gaming console has a metal top plate of sufficient width and length to cover the exterior opening of the expansion slot. The top plate has fins on its upper surface that extend at a diagonal across the longitudinal extent of the top plate. The heat sink further includes a metal bulk body connected to the bottom of the top plate and having a sufficient width and length to nearly fill the interior of the expansion slot and a thickness so that when the heat sink is mounted on the SSD storage device, the top plate is positioned above the upper edge of the expansion slot. A thermal adhesive is provided on the bottom of the bulk body for fastening the heat sink to the top of the SSD storage device.

A memory control component encodes over-capacity data into an error correction code generated for and stored in association with an application data block, inferentially recovering the over-capacity data during application data block read-back by comparing error syndromes generated in detection / correction operations for respective combinations of each possible value of the over-capacity data and the read-back application data block.

The present application relates to the technical field of servers and discloses a server operation starting method and device, a server, and a storage medium. The method comprises: in a power-on self-test process of a server, on the basis of an external loading sequence, using a target configuration space to load an extended memory of each target external device; in response to detecting that the space of the target configuration space is insufficient, detecting the remaining space of another module in a preset addressing space; and in response to determining that the remaining space meets a demand space corresponding to the target configuration space, re-allocating the preset addressing space, to make the configuration space reallocated to an external device loading module be greater than or equal to the sum of the target configuration space and the demand space. According to the present application, when the configuration space of the external device loading module is insufficient, memory resources can be reintegrated on the basis of the use condition of the configuration space allocated to each module, it is guaranteed that limited memory resources can be utilized to the maximum extent, and the occurrence of an external device being unable to be used normally is reduced.

The present application provides an integrated memory expansion device and a computing device. The integrated memory expansion device is used for expanding memory for a server. The integrated memory expansion device comprises a case, a first circuit board, a first connection interface, a plurality of first memory slots, and a plurality of first memory expansion cards, wherein the first circuit board, the first connection interface, and the plurality of first memory slots are all arranged in the case; the plurality of first memory slots are arranged at intervals on the first circuit board; the first connection interface is electrically connected to the first circuit board; the first connection interface is exposed out of the outer surface of the case and is used for being connected to the server; the case is provided with a plurality of first inserting holes; the interior and the exterior of the case are communicated by means of each first inserting hole; each first memory expansion card passes through one first inserting hole and is detachably inserted into one first memory slot. The integrated memory expansion device can provide a large amount of memory space for an electronic device, thereby meeting the requirements of the computing device for scenarios such as big data processing.

The invention provides a memory access reordering processing method, system and device based on an SIMT architecture and a medium, and belongs to the technical field of memory access optimization. The method comprises the following steps: configuring a memory access reordering unit in a parallel processing unit assembly line based on the SIMT architecture, and constructing a cache reordering unit between cache unit hierarchies; incrementally modifying a decoding and executing module in the parallel processing unit and expanding a memory access optimization instruction and decoding logic; setting a cooperative work flow of the two units; constructing a functional architecture of the cache reordering unit, and realizing data prefetching, classified storage and on-demand feedback through functional configuration; dividing a software instruction kernel into a memory access regular kernel and a memory access irregular kernel, and configuring a software and hardware processing mechanism for the memory access regular kernel and the memory access irregular kernel; by configuring software side parameters and hardware side instructions for the irregular memory access kernel, a parallel processing unit is controlled to dynamically reorder memory access requests, and logically adjacent address indexes are distributed to the same processing unit in a centralized manner for execution.

The invention provides an embedded Linux system hardware self-adaption method based on an extended memory and an electronic terminal. The method comprises the following steps: acquiring hardware configuration information of an embedded Linux system; according to the hardware configuration information, storing a boot0 program, a device user-defined initialization program and a kernel device tree in a preset storage area of the extended memory; when the system is powered on and started, the microprocessor is set to be started from the extended memory through hardware circuit management; the bootloader program loads a kernel device tree to a preset address of a memory from the extended memory; and the kernel adapts to the current hardware configuration according to the transmitted memory address of the kernel device tree to complete starting. According to the adaptive method provided by the invention, the boot program and the configuration information are stored by the extended memory, so that the hardware configuration diversification of the embedded Linux system is realized.

Disclosed are a network interface card device, a network data transmission method, apparatus, and system, a device, and a medium, which are applied to the field of Internet technologies. The network interface card device includes a programmable device, which constructs a network platform based on a memory expansion method, and the network platform includes a network interface, a target memory, and a network component. The programmable device is connected to a network through the network interface, and exchanges data with a host by the memory expansion method. The host, based on the memory expansion method, configures the target memory of the programmable device as an extended memory of the host, for storing received target network data belonging to a network interface card processed packet type, or to-be-sent network data of the host.

The application discloses a kind of federated multi-task continuous learning methods and systems for edge computing, and the method is constructed and maintained by central server dynamic evolution orthogonal main subspace as long-term memory library;Each edge node generates safe update that does not interfere with historical knowledge after local training, by projecting model update to the orthogonal direction of corresponding space;Server then adopts super-collaborative aggregation algorithm to fuse the safe update of each edge node to coordinate the knowledge transfer between multi-task;Finally update global model and expand memory library.The application effectively realizes the interference-free accumulation of knowledge in time sequence and spatial dimension, and adapts the resource constraints of edge node, to provide an efficient continuous learning solution for edge intelligence.

Aspects of this disclosure improve modification of requested web content by utilizing an expanded memory buffer of a proxy server. A method may include receiving, by a proxy, web content requested by an application of a user device; initializing, by the proxy, a memory buffer of a first size to store a header of the web content; determining, by the proxy, a set of filtering rules associated with the user of the user device; determining, by the proxy, modified web content in accordance with the set of filtering rules, wherein the determining comprises, when the filtering rules specify modification of body content of the web content, performing operations comprising: expanding the memory buffer to a second size larger than the first size. Other aspects are also disclosed.

Described herein are systems and methods for dynamically configuring memory using Optical Circuit Switching (OCS). As electrical processing units such as accelerators are limited by their available bandwidth, providing disaggregated memory can help expand memory and enable better processing performance. Providing OCS devices to dynamically reconfigure processor-to-processor and processor-to-memory connections enables flexible reconfiguration of the disaggregated memory and improve performance of the system.

The present disclosure discloses a data read and write method. The method is applied to a logical management controller, where the logical management controller communicates with a central processing unit (CPU) and at least two expanded memory controllers respectively based on a compute express link (CXL) protocol, the logical management controller includes a request parsing module, an address decoding module, a request decomposition module and a request allocation module, and the method includes: parsing a received data read and write request for target data to obtain a local command; performing command parsing on the local command to determine location information for reading and writing data; generating a plurality of data read and write sub-requests based on the location information; sending the plurality of data read and write sub-requests to target expanded memory controllers; and controlling the target expanded memory controllers to perform data read and write operations in parallel according to the plurality of data read and write sub-requests.

The invention discloses an application-awareness-free memory longitudinal capacity expansion method. The method comprises the following steps: determining a basic memory boundary of a Serverless instance; according to the basic memory boundary of the Serverless instance, dynamically distributing continuous memory blocks for the Serverless instance; when the actual memory demand exceeds the basic memory boundary, triggering a memory expansion mechanism; the method comprises the following steps of: transferring an isolation domain which is operated by a Serverless application to the operation time of Serverless through a Cinvoke mechanism; when the Serverless runs, the number of memory blocks of a single Serverless instance is increased, so that the longitudinal capacity expansion of the memory is realized; and initializing the new memory block, and registering the new memory block into memory management of the LibOS. According to the method, the performance advantage of longitudinal capacity expansion of the memory is exerted while the isolation of the Serverless application is kept.

The embodiment of the invention provides a resource capacity expansion method and device, electronic equipment and a storage medium. The resource capacity expansion method comprises the steps that in response to a calling event of a set function, the set function is called through a proxy function, and the set function comprises an application programming interface related to a thread key; under the condition that calling of the set function fails, the set function is processed based on a target array associated with the set function; wherein the target array is an expansion resource stored in an expanded memory, and is used for storing contents associated with the set function. The technical problem caused by unreasonable use of thread key resources in troubleshooting is solved, under the condition that call of the set function fails, the set function is processed by expanding the target array in the memory, that is, the set function is processed by expanding the resources, use of the thread key resources is prevented from being analyzed, and the service life of the set function is prolonged. And the response speed of setting function calling is improved.

Provided in the embodiments of the present disclosure are a device operation method, system and apparatus, and a non-volatile readable storage medium and an electronic device. The method comprises: during the process of executing a power-on self-test on a server, acquiring a plurality of peripheral devices connected to the server, and memories of expanded memories of respective ones of the plurality of peripheral devices; determining whether the memories of the expanded memories of the plurality of peripheral devices meet a preset memory condition of a basic input output system in the server; when the memories of the expanded memories do not meet the preset memory condition, determining a plurality of candidate device sequences according to the plurality of peripheral devices; and determining a target device sequence from among the plurality of candidate device sequences, and loading and running the multiple target devices in the target device sequence.

Various embodiments described herein provide for expanding the size of memory cells of a memory device, such as the size of codewords of a page of the memory device, where the memory device can be included in a memory system. In particular, some embodiments implement expanding (e.g., increasing) the size of the memory cells (e.g., codewords) to store more data, such as more host data (e.g., user data) and protection data (e.g., parity data) within the memory cells, while using memory cell storage slots (e.g., codeword storage slots in a page) that are smaller than the expanded memory cells.

A memory management method for a device, and a memory management device and a computing system. The method comprises: determining a plurality of application scenarios of the device; and according to the number of physical memory blocks required by each hardware unit in each application scenario and according to an established mapping relationship between system memory blocks in system memory and physical memory blocks in physical memory, determining system memory blocks allocated to corresponding hardware units, the system memory comprising the physical memory and expanded memory corresponding to the physical memory; wherein the system memory blocks allocated to all the hardware units running in a same application scenario are respectively mapped to different physical memory blocks, or in the system memory blocks allocated to at least two hardware units respectively running in different application scenarios, the system memory block of at least one of the different application scenarios and the system memory block of the other application scenario are mapped to the same physical memory block.

The application discloses a kind of dynamic adjustment method and terminal of task memory, monitor and calculate the average task processing rate of each subtask of pending task under historical condition;When the real-time execution data of pending task is obtained, if pending task has not been set fast task label, whether the current pending task exceeds the average task processing rate of preset proportion subtask, if yes, set fast task label for pending task;If pending task has been set fast task label, then increase the memory threshold of pending task according to preset proportion. In this way, the real-time processing rate of a task can be compared with the historical average processing rate to identify tasks that can improve processing speed by expanding memory, and dynamically configure appropriate memory threshold for the task. The dynamic adjustment of task memory can improve task processing speed and efficiency.

A memory expansion method and apparatus, a server system, an electronic device, and a storage medium, which relate to the technical field of computers. The server system comprises a plurality of servers and a memory server. The servers comprise a main server and a plurality of sub-servers. The memory server comprises a switch and a plurality of memory expansion devices. The plurality of memory expansion devices are connected to the switch, the plurality of servers are connected to the switch, and each memory expansion device comprises an expanded memory. The memory expansion method comprises: receiving a memory application request from a sub-server; on the basis of a memory size applied for in the memory application request, determining a target memory expansion device among a plurality of memory expansion devices; and sending resource information of the target memory expansion device to the sub-server, so that the sub-server uses an expanded memory in the target memory expansion device.

The utility model relates to the technical field of cloud storage devices, in particular to a cloud storage device. The cloud storage device comprises a shell, a first hard disk and an installation frame. The installation frame is installed in the shell, a hard disk insertion space is formed in the installation frame, the first hard disk is detachably inserted in the hard disk insertion space, the installation frame comprises a first side plate, and a memory expansion slot is formed in the inner side face of the first side plate and used for installing a second hard disk for expanding a memory. The cloud storage device is provided with the installation frame, the installation frame comprises the first side plate, the internal memory expansion slot position is arranged on the inner side face of the first side plate, and the internal memory expansion slot position can be used for installing the second hard disk for expanding the internal memory, so that the storage space of the cloud storage device can be increased when the storage space of the original first hard disk of the cloud storage device is insufficient. The memory is expanded after the original memory space of the cloud storage device is insufficient, and a new cloud storage device does not need to be added, so that the use cost of a user is reduced, and the use flexibility is high.

Memory system and methods of fabrication are described in which memory capacity and / or bandwidth can be expanded. In some implementations expansion may be accomplished with inclusion of custom buffer base dies, or other suitable components including network routing connecting multiple memory die stacks. In some implementations expansion may be accomplished with integration of vertically oriented memory die stacks.

The present application discloses a distributed computing method, apparatus, device and system and a readable storage medium. The distributed computing method is applied to a controller of a distributed accelerator cluster and includes: acquiring information of accelerators in the distributed accelerator cluster; establishing an accelerator direct-connection pair according to the information of the accelerators; and in response to receiving a service task, dividing the service task into computing tasks and distributing the computing tasks to an idle target accelerator having an application computing logic matching the type of the corresponding computing tasks, wherein the accelerator direct-connection pair includes two accelerators that are directly connected to each other, and at least one of the two accelerators is a first accelerator that supports a computer express link protocol and has an extended memory, and / or the two accelerators have the same application computing logic.

A memory structure includes randomly accessible, channel-all-around ferroelectric memory transistors organized as horizontal NOR memory strings. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film ferroelectric memory transistors. The three-dimensional memory stacks are manufactured in a process that includes forming holes in a multi-layer film stack for forming local word line structures and slit trenches to divide the film stack into memory stacks including local word line structures formed therein. The memory structure of channel-all-around ferroelectric memory transistors enables a scalable construction for realizing a high density, high capacity memory device.

Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example apparatus can include a plurality of computing devices. Each of the computing devices can include a processing unit configured to perform an operation on a block of data, and a memory array configured as a cache for each respective processing unit. The example apparatus can further include a first communication subsystem coupled to a host and to each of the plurality of communication subsystems. The example apparatus can further include a plurality of second communication subsystems coupled to each of the plurality of computing devices. Each of the plurality of computing devices can be configured to receive a request from the host, send a command to execute at least a portion of the operation, and receive a result of performing the operation from the at least one hardware accelerator.

The testing system comprises a processor and a local memory on a motherboard and an extension memory device under test (DUT). The local memory corresponds to a first address range within system memory and the extension memory DUT associated with a second address range within the system memory. The processor is operable to direct write latency testing of the extension memory DUT, including recording write latency measurement values. The recording can be done in a frequency table and the frequency table can be visualized (e.g., rendered, etc.) on a display. The testing comprises non-temporal write instructions that bypass processor caches. The extension memory DUT is compatible with a compute express link (CXL) protocol.

A system includes: a group of memory resources including a first memory node and a second memory node, the first memory node being connected to the second memory node over a switching fabric; and a synchronous clock source connected to the first memory node and the second memory node, the synchronous clock source to provide a synchronized clock signal to the first memory node and the second memory node to synchronize the first memory node with the second memory node. The first memory node and the second memory node are to encode memory data and decode encoded memory data using the synchronized clock signal.

Apparatuses and methods for trusted access to extended memory through a plurality of potential heterogeneous compute nodes are disclosed. A plurality of roots of trust are described under a super root of trust (SROT). One embodiment comprises: a core of a host processor; a host processor memory subsystem to provide access to a host processor memory; a home agent to provide access by the core to the host processor memory subsystem and the extension memory subsystem; and a source address decoder to decode the memory requests generated from the plurality of cores to determine whether the memory requests are to be directed to the host processor memory subsystem or the extended memory subsystem. The host-based security circuitry encrypts and decrypts a memory request directed to the extended memory subsystem, the host-based security circuitry performing encryption and decryption based on a second key stored in a cache maintained by the host-based security circuitry.

Memory system and methods of fabrication are described in which memory capacity and / or bandwidth can be expanded. In some implementations expansion may be accomplished with inclusion of custom buffer base dies, or other suitable components including network routing connecting multiple memory die stacks. In some implementations expansion may be accomplished with integration of vertically oriented memory die stacks.