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42 results about "Expanded memory" patented technology
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In DOS memory management, expanded memory is a system of bank switching that provided additional memory to DOS programs beyond the limit of conventional memory (640 KB). Expanded memory is an umbrella term for several incompatible technology variants. The most widely used variant was the Expanded Memory Specification (EMS), which was developed jointly by Lotus Software, Intel, and Microsoft, so that this specification was sometimes referred to as "LIM EMS". LIM EMS had several versions. The first widely implemented version was EMS 3.2, which supported up to 8 MB of expanded memory and uses parts of the address space normally dedicated to communication with peripherals (upper memory) to map portions of the expanded memory. EEMS, an expanded-memory management standard competing with LIM EMS 3.x, was developed by AST Research, Quadram and Ashton-Tate ("AQA"); it could map any area of the lower 1 MB. EEMS ultimately was incorporated in LIM EMS 4.0, which supported up to 32 MB of expanded memory and provided some support for DOS multitasking as well. IBM, however, created its own expanded-memory standard called XMA.
Network interface card device, network data transmission method, apparatus, and system, device, and medium
Disclosed are a network interface card device, a network data transmission method, apparatus, and system, a device, and a medium, which are applied to the field of Internet technologies. The network interface card device includes a programmable device, which constructs a network platform based on a memory expansion method, and the network platform includes a network interface, a target memory, and a network component. The programmable device is connected to a network through the network interface, and exchanges data with a host by the memory expansion method. The host, based on the memory expansion method, configures the target memory of the programmable device as an extended memory of the host, for storing received target network data belonging to a network interface card processed packet type, or to-be-sent network data of the host.
Owner:INSPUR (BEIJING) ELECTRONICS INFORMATION IND CO LTD
A federated multi-task continual learning method and system for edge computing
The application discloses a kind of federated multi-task continuous learning methods and systems for edge computing, and the method is constructed and maintained by central server dynamic evolution orthogonal main subspace as long-term memory library;Each edge node generates safe update that does not interfere with historical knowledge after local training, by projecting model update to the orthogonal direction of corresponding space;Server then adopts super-collaborative aggregation algorithm to fuse the safe update of each edge node to coordinate the knowledge transfer between multi-task;Finally update global model and expand memory library.The application effectively realizes the interference-free accumulation of knowledge in time sequence and spatial dimension, and adapts the resource constraints of edge node, to provide an efficient continuous learning solution for edge intelligence.
Owner:FUJIAN NORMAL UNIV +2
Proxy server with dynamic memory buffer
Aspects of this disclosure improve modification of requested web content by utilizing an expanded memory buffer of a proxy server. A method may include receiving, by a proxy, web content requested by an application of a user device; initializing, by the proxy, a memory buffer of a first size to store a header of the web content; determining, by the proxy, a set of filtering rules associated with the user of the user device; determining, by the proxy, modified web content in accordance with the set of filtering rules, wherein the determining comprises, when the filtering rules specify modification of body content of the web content, performing operations comprising: expanding the memory buffer to a second size larger than the first size. Other aspects are also disclosed.
Owner:LIGHTSPEED SOLUTIONS LLC
Methods and techniques for optical circuit switching
PendingUS20260110848A1Multiplex system selection arrangementsCoupling light guidesOptical circuit switchingEmbedded system
Described herein are systems and methods for dynamically configuring memory using Optical Circuit Switching (OCS). As electrical processing units such as accelerators are limited by their available bandwidth, providing disaggregated memory can help expand memory and enable better processing performance. Providing OCS devices to dynamically reconfigure processor-to-processor and processor-to-memory connections enables flexible reconfiguration of the disaggregated memory and improve performance of the system.
Owner:LIGHTMATTER INC
Data read-write method and system, and device and storage medium
The present disclosure discloses a data read and write method. The method is applied to a logical management controller, where the logical management controller communicates with a central processing unit (CPU) and at least two expanded memory controllers respectively based on a compute express link (CXL) protocol, the logical management controller includes a request parsing module, an address decoding module, a request decomposition module and a request allocation module, and the method includes: parsing a received data read and write request for target data to obtain a local command; performing command parsing on the local command to determine location information for reading and writing data; generating a plurality of data read and write sub-requests based on the location information; sending the plurality of data read and write sub-requests to target expanded memory controllers; and controlling the target expanded memory controllers to perform data read and write operations in parallel according to the plurality of data read and write sub-requests.
Owner:INSPUR SUZHOU INTELLIGENT TECH CO LTD
Device operation method, system and apparatus, and non-volatile readable storage medium and electronic device
Provided in the embodiments of the present disclosure are a device operation method, system and apparatus, and a non-volatile readable storage medium and an electronic device. The method comprises: during the process of executing a power-on self-test on a server, acquiring a plurality of peripheral devices connected to the server, and memories of expanded memories of respective ones of the plurality of peripheral devices; determining whether the memories of the expanded memories of the plurality of peripheral devices meet a preset memory condition of a basic input output system in the server; when the memories of the expanded memories do not meet the preset memory condition, determining a plurality of candidate device sequences according to the plurality of peripheral devices; and determining a target device sequence from among the plurality of candidate device sequences, and loading and running the multiple target devices in the target device sequence.
Owner:INSPUR SUZHOU INTELLIGENT TECH CO LTD
Size of an extended memory unit
ActiveCN114968649BRedundant data error correctionInput/output processes for data processingMemory cellParallel computing
Various embodiments described herein provide for expanding the size of memory cells of a memory device, such as the size of codewords of a page of the memory device, where the memory device can be included in a memory system. In particular, some embodiments implement expanding (e.g., increasing) the size of the memory cells (e.g., codewords) to store more data, such as more host data (e.g., user data) and protection data (e.g., parity data) within the memory cells, while using memory cell storage slots (e.g., codeword storage slots in a page) that are smaller than the expanded memory cells.
Owner:MICRON TECHNOLOGY INC
A method for dynamically adjusting task memory and a terminal
The application discloses a kind of dynamic adjustment method and terminal of task memory, monitor and calculate the average task processing rate of each subtask of pending task under historical condition;When the real-time execution data of pending task is obtained, if pending task has not been set fast task label, whether the current pending task exceeds the average task processing rate of preset proportion subtask, if yes, set fast task label for pending task;If pending task has been set fast task label, then increase the memory threshold of pending task according to preset proportion. In this way, the real-time processing rate of a task can be compared with the historical average processing rate to identify tasks that can improve processing speed by expanding memory, and dynamically configure appropriate memory threshold for the task. The dynamic adjustment of task memory can improve task processing speed and efficiency.
Owner:福建天晴在线互动科技有限公司
Scalable capacity and bandwidth expansion for memory systems
PCT designated stageWO2026072243A1Semiconductor/solid-state device detailsSolid-state devicesComputer architectureEngineering
Memory system and methods of fabrication are described in which memory capacity and / or bandwidth can be expanded. In some implementations expansion may be accomplished with inclusion of custom buffer base dies, or other suitable components including network routing connecting multiple memory die stacks. In some implementations expansion may be accomplished with integration of vertically oriented memory die stacks.
Owner:APPLE INC
Distributed computing method, apparatus, device and system and readable storage medium
PendingUS20260030055A1Program initiation/switchingResource allocationController (computing)Computer engineering
The present application discloses a distributed computing method, apparatus, device and system and a readable storage medium. The distributed computing method is applied to a controller of a distributed accelerator cluster and includes: acquiring information of accelerators in the distributed accelerator cluster; establishing an accelerator direct-connection pair according to the information of the accelerators; and in response to receiving a service task, dividing the service task into computing tasks and distributing the computing tasks to an idle target accelerator having an application computing logic matching the type of the corresponding computing tasks, wherein the accelerator direct-connection pair includes two accelerators that are directly connected to each other, and at least one of the two accelerators is a first accelerator that supports a computer express link protocol and has an extended memory, and / or the two accelerators have the same application computing logic.
Owner:INSPUR (BEIJING) ELECTRONICS INFORMATION IND CO LTD
Write latency testing systems and methods
ActiveUS20260038618A1Faulty hardware testing methodsStatic storageComputer architectureAssociative processor
The testing system comprises a processor and a local memory on a motherboard and an extension memory device under test (DUT). The local memory corresponds to a first address range within system memory and the extension memory DUT associated with a second address range within the system memory. The processor is operable to direct write latency testing of the extension memory DUT, including recording write latency measurement values. The recording can be done in a frequency table and the frequency table can be visualized (e.g., rendered, etc.) on a display. The testing comprises non-temporal write instructions that bypass processor caches. The extension memory DUT is compatible with a compute express link (CXL) protocol.
Owner:ADVANTEST CORP
Systems and methods for synchronous cell switching for scalable memory
ActiveUS12468628B2Memory architecture accessing/allocationMemory systemsComputer architectureEngineering
A system includes: a group of memory resources including a first memory node and a second memory node, the first memory node being connected to the second memory node over a switching fabric; and a synchronous clock source connected to the first memory node and the second memory node, the synchronous clock source to provide a synchronized clock signal to the first memory node and the second memory node to synchronize the first memory node with the second memory node. The first memory node and the second memory node are to encode memory data and decode encoded memory data using the synchronized clock signal.
Owner:SAMSUNG ELECTRONICS CO LTD
Apparatus and method for trusted access to extended memory through multiple potential heterogeneous compute nodes
PendingCN120654277AMemory architecture accessing/allocationDigital data protectionComputer architectureEngineering
Apparatuses and methods for trusted access to extended memory through a plurality of potential heterogeneous compute nodes are disclosed. A plurality of roots of trust are described under a super root of trust (SROT). One embodiment comprises: a core of a host processor; a host processor memory subsystem to provide access to a host processor memory; a home agent to provide access by the core to the host processor memory subsystem and the extension memory subsystem; and a source address decoder to decode the memory requests generated from the plurality of cores to determine whether the memory requests are to be directed to the host processor memory subsystem or the extended memory subsystem. The host-based security circuitry encrypts and decrypts a memory request directed to the extended memory subsystem, the host-based security circuitry performing encryption and decryption based on a second key stored in a cache maintained by the host-based security circuitry.
Owner:INTEL CORP
Scalable Capacity and Bandwidth Expansion for Memory Systems
Memory system and methods of fabrication are described in which memory capacity and / or bandwidth can be expanded. In some implementations expansion may be accomplished with inclusion of custom buffer base dies, or other suitable components including network routing connecting multiple memory die stacks. In some implementations expansion may be accomplished with integration of vertically oriented memory die stacks.
Owner:APPLE INC
External instrument system for vehicles, vehicle instrument and its function extender
This application discloses an external vehicle instrument system, a vehicle instrument, and its function extender, applicable to the field of vehicle manufacturing technology. The system includes an instrument body and a function extender with a matching shape. The instrument body includes a controller, a main communication module, an electrical connection module, and a loop detection module. The function extender includes a secondary communication module and an extended memory. The instrument body and the function extender are connected via the electrical connection module, and the loop detection module detects whether the function extender is connected to the instrument body. The instrument body communicates with the secondary communication module of the function extender via the main communication module and reads data from the extended memory. The controller executes corresponding data update tasks based on the acquired information to be extended and / or data to be upgraded, effectively improving the practicality of the external vehicle instrument and meeting users' customization needs.
Owner:HIGO TECH (SUZHOU) CO LTD
Three-dimensional memory device including discrete charge storage elements and method of making thereof
An alternating stack of insulating layers and electrically conductive layers is formed over a substrate, and a memory opening vertically extends through the alternating stack. The memory opening is laterally expanded at levels of the insulating layers. At least one blocking dielectric layer is formed in the memory opening. A first vertical stack of discrete charge storage elements is formed at levels of the electrically conductive layers. A second vertical stack of discrete dielectric material portions is formed at the levels of the insulating layers. A tunneling dielectric layer is formed over the first vertical stack and the second vertical stack. A vertical semiconductor channel is formed on the tunneling dielectric layer.
Owner:SANDISK TECHNOLOGIES LLC
Memory expansion system and method, switch and memory pool
The embodiment of the invention provides a memory expansion system and method, a switch and a memory pool, the system comprises a computing node supporting a computer high-speed interconnection protocol, the switch and the memory pool, the switch comprises a switch chip and a controller used for managing the switch chip, a processor in the computing node is connected with an uplink port of the switch chip, and the processor is connected with the memory pool. The memory pool comprises a plurality of extended memory media, and the plurality of extended memory media are respectively connected with different downlink ports of the switch chip. And the controller is used for configuring a corresponding relation between an uplink port and a downlink port of the switching chip so as to reflect the memory which can be expanded and used by the processor in the computing node. In the scheme, a memory pool which is shared by a plurality of computing nodes and supports the CXL protocol is arranged, and an independent switch which supports the CXL protocol is arranged, so that the aim of flexibly expanding memories used by processors in the computing nodes is fulfilled through the switch.
Owner:CLOUD INTELLIGENCE ASSETS HOLDING (SINGAPORE) PTE LTD
Write latency testing systems and methods
The testing system comprises a processor and a local memory on a motherboard and an extension memory device under test (DUT). The local memory corresponds to a first address range within system memory and the extension memory DUT associated with a second address range within the system memory. The processor is operable to direct write latency testing of the extension memory DUT, including recording write latency measurement values. The recording can be done in a frequency table and the frequency table can be visualized (e.g., rendered, etc.) on a display. The testing comprises non-temporal write instructions that bypass processor caches. The extension memory DUT is compatible with a compute express link (CXL) protocol.
Owner:ADVANTEST CORP
Systems and methods for port based routing for scalable memory
A system including: a first memory layer including: a first memory node of a memory pool; and a second memory node of the memory pool, the second memory node being connected to the first memory node by one link in the first memory layer; and a switch to provide access to the first memory node from the second memory node based on: a first identifier corresponding to the first memory layer; and a second identifier corresponding to a location of the first memory node in the memory pool.
Owner:SAMSUNG ELECTRONICS CO LTD
Circuit for performing analog calibration for a scalable multi-voltage memory interface driver
A circuit for calibrating analog signals on a scalable memory interface driver is provided. The circuit includes: PMOS and NMOS drivers; a variable gate voltage generation circuit; a pull-up stop signal generation circuit; and a pull-down stop signal generation circuit. The circuit is configured to: provide a first variable voltage to the PMOS driver from the variable gate voltage generation circuit; stop the first variable voltage from changing by disconnecting a first current source according to using a pull-up calibration stop signal, based on identifying that the first driver output is greater than a reference value; provide a second variable voltage to the NMOS driver from the variable gate voltage generation circuit; and stop the second variable voltage from changing by disconnecting a second current source according to using a pull-down calibration stop signal, based on the second driver output from the NMOS driver being less than the reference value.
Owner:SAMSUNG ELECTRONICS CO LTD
System and method for port-based routing of expandable memory
A system comprising: a first memory layer comprising a first memory node of a memory pool; and a second memory node of the memory pool, the second memory node being connected to the first memory node by a link in the first memory layer; and a switch to provide access to the first memory node from the second memory node based on: a first identifier corresponding to the first memory layer; and a second identifier corresponding to a location of the first memory node in the memory pool.
Owner:SAMSUNG ELECTRONICS CO LTD
X-ray imaging system with fluoroscopy feature, portable x-ray plane detector, photography platform, and fluoroscopic table
To carry out fluoroscopy using a portable X-ray plane detector (FPD) that is thin and light-weight.SOLUTION: A photography platform includes a cradle that holds an inserted X-ray plane detector. The X-ray plane detector includes a signal processing part that creates detected data for image formation by processing signals readout from an X-ray detection part. The cradle includes a signal processing feature expansion part connected to the signal processing part of the inserted X-ray plane detector. The signal processing part includes a memory, and the signal processing feature expansion part includes an expanded memory.The signal processing part creates detected data for one image by using the memory during imaging, and repetitively creates detected data at a predetermined frame rate by using the memory and the expanded memory during fluoroscopy.SELECTED DRAWING: Figure 3
Owner:FUJIFILM CORP
Memory configuration method and multi-head single-logic device (MH-SLD)
The present application provides a memory configuration method and a multi-head single-logic device (MH-SLD). The method is applied to an MH-SLD, and comprises: receiving a memory configuration request, wherein the memory configuration request comprises memory configuration information corresponding to at least two heads, and the memory configuration information corresponding to the at least two heads indicates that the at least two heads correspond to a same address range of a CXL expanded memory; parsing the memory configuration request to obtain memory mapping ranges corresponding to the at least two heads; and on the basis of the memory mapping ranges corresponding to the at least two heads, configuring memory mapping ranges corresponding to the at least two heads. The method enables configuration of memory mapping ranges for at least two heads, and the memory mapping ranges for the at least two heads have an overlapping region, so that the same CXL expanded memory segment can be accessed via the at least two heads, thereby enabling host nodes connected to the at least two heads to access the same CXL memory segment.
Owner:XFUSION DIGITAL TECH CO LTD
A memory expansion module and a PCIE module
ActiveCN119562440BCoupling device connectionsPrinted circuits structural associationsElectrical connectionPrinted circuit board
The specification provides a memory expansion module and a PCIE module, and relates to the technical field of electronics. The memory expansion module comprises: a first printed circuit board, a memory expansion chip and a heat sink covering the memory expansion chip are arranged on the first printed circuit board, and a gold finger for plugging a PCIE interface is arranged on one side of the first printed circuit board; a second printed circuit board, at least two memory slots are arranged on the second printed circuit board, the memory slots are arranged on the two side surfaces of the second printed circuit board, and memories are arranged on the memory slots in a plug-pull manner; a rotating mechanism is fixed to the first printed circuit board and the second printed circuit board, and the second printed circuit board is arranged in a rotating manner relative to the first printed circuit board through the rotating mechanism; and an electrical connection mechanism is arranged between the first printed circuit board and the second printed circuit board, and the memory expansion chip and the memory slots are electrically connected. Through the above structure, the maintenance efficiency of the expanded memory in the electronic equipment can be improved.
Owner:NEW H3C TECH CO LTD
Memory structure of annular channel ferroelectric memory transistor of three-dimensional NOR memory string and manufacturing method
A memory structure is provided that includes a random accessible annular channel ferroelectric memory transistor organized as a horizontal NOR memory string. The NOR memory strings are formed in a plurality of scalable memory stacks of thin film ferroelectric memory transistors over a semiconductor substrate. The three-dimensional memory stack is fabricated in a process that includes forming holes in a multilayer film stack for forming local word line structures and forming slit trenches to divide the film stack into memory stacks including local word line structures formed therein. The memory structures of the annular channel ferroelectric memory transistors enable scalable configurations for implementing high density, high capacity memory devices.
Owner:SUNRISE MEMORY CORP
Systems and methods for extended memory
PendingUS20260003525A1Memory architecture accessing/allocationInput/output to record carriersComputer architectureExtended memory
Systems and methods for extended memory are disclosed. An apparatus for extended memory may include a first processing device; a second processing device; a first memory device; and a second memory device. A first logical memory space and a second logical memory space are configured to be allocated for respectively the first processing device and the second processing device. The first logical memory space and the second logical memory space are further configured to be mapped to a first physical memory space of one of the first memory device or the second memory device.
Owner:SAMSUNG ELECTRONICS CO LTD
Extended memory architecture
ActiveCN113851168BDigital data processing detailsError detection/correctionComputer architectureEngineering
The present disclosure relates to extended memory architectures. An example device can include a plurality of compute devices. Each of the compute devices can include a processing unit configured to perform an operation on a block of data and a memory array configured as a cache for each respective processing unit. The example device can further include a first communication subsystem coupled to a host and each of the plurality of compute devices. The example device can further include a plurality of second communication subsystems coupled to each of the plurality of compute devices. Each of the plurality of compute devices can be configured to receive a request from the host, send a command to perform at least a portion of the operation, and receive a result of performing the operation from the at least one hardware accelerator.
Owner:MICRON TECHNOLOGY INC
Data processing system, method, and computer system
The present application relates to the field of computer systems, and discloses a data processing system, a method, and a computer system. In order to solve the problems of long access path and high access delay for accessing an expanded memory, the data processing system comprises a processing board and a memory expansion board. The processing board is provided with a processing core and a first controller, and the memory expansion board is provided with a storage component and a control component. The present application can enable a processing board to directly access a storage component on a memory expansion board, and memory copying does not need to be performed by means of a server host, thereby reducing the degree of coupling between the processing board and the server host when accessing an expanded memory. While effectively expanding the memory of the processing board, an access path of the processing board for the expanded memory is shortened and access delay is reduced, thereby reducing a communication bottleneck in the training process of a pre-trained model.
Owner:LANGCHAO ELECTRONIC INFORMATION IND CO LTD
3D bit cost scalable memory
A 3D bit cost scalable memory device includes a stack of layers and a via electrode extending vertically through the stack of layers. The layers include a controllable conductivity layer and an electrode layer. The electrode layer has a conductor portion and a separator portion that separates the via electrode from the conductor portion of the electrode layer. At least a storage portion of the controllable conductivity layer is in electrical series between the via electrode and the conductor portion of the electrode layer. The via electrode comprises, for example, tungsten (W). The controllable conductivity layer comprises, for example, an ovonic threshold switch material. The conductor portion of the electrode layer comprises, for example, carbon (C).
Owner:MACRONIX INTERNATIONAL CO LTD
High bandwidth extended memory in a parallel processing system
Various embodiments include techniques for accessing extended memory in a parallel processing system via a high-bandwidth path to extended memory residing on a central processing unit. The disclosed extended memory system extends the directly addressable high-bandwidth memory local to a parallel processing system and avoids the performance penalties associated with low-bandwidth system memory. As a result, execution threads that are highly parallelizable and access a large memory space execute with increased performance on a parallel processing system relative to prior approaches.
Owner:NVIDIA CORP