39 results about "Custom integrated circuits" patented technology

A method and apparatus for adaptively adjusting the operating voltage of an integrated circuit in response to tester-to-system variations, worst-case testing techniques, process variations, temperature variations, or reliability wearout mechanisms. The minimum operating voltage of an integrated circuit is determined either during external testing of the integrated circuit or during built-in-self-testing. The minimum operating voltage is transmitted to a variable voltage regulator where it is used to set the output of the regulator. The output of the regulator supplies the integrated circuit with its operating voltage. This technique enables tailoring of the operating voltage of integrated circuits on a part-by-part basis which results in power consumption optimization by adapting operating voltage in response to tester-to-system variations, worst-case testing techniques, process variations, temperature variations or reliability wearout mechanisms. Alternatively, the invention enables adaptive adjustment of the operating frequency of an integrated circuit. The invention enables system designers to adaptively optimize either system performance or power consumption on a part-by-part basis in response to tester-to system variations, worst-case testing techniques, process variations, temperature variations or reliability wearout mechanisms.

A system for performing device-specific testing and acquiring parametric data on custom integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The testing system includes a device test structure integrated into unused backfill space in an ASIC design which tests a set of dummy devices that are identical to some of those of the ASIC. The device test structure includes control logic for designating the type of test and which device types to activate (e.g. pFETs or nFETs), a protection circuit for protecting the SPM when the test is inactive, an isolation circuit for isolating the devices under test (DUT) from any leakage current during test, and a decode circuit for providing test input (e.g. voltages) to the DUT. By controlling which devices to test and the voltage conditions of those devices, the system calculates the relative product yield and health of the line on a die by die basis.

Automated design of a custom integrated circuit based on algorithmic process as input and using highly automated tools that requires virtually no human involvement is disclosed. The method includes receiving a specification of the custom integrated circuit including computer readable code and constraints on the custom integrated circuit; generating a computer-architecture for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over processing blocks to reduce hot spots; continuously evaluating and optimizing one or more factors including physical implementation, and local and global area, timing, or power at an architecture level above RTL or gate-level synthesis; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication.

An integrated circuit, a method for making an integrated circuit product, and methods for customizing an integrated circuit are disclosed. Integrated circuit elements including programmable elements, such as fuses, PROMs, RRAMs, MRAMs, or the like, are formed on the frontside of a substrate. Vias are formed through the substrate from its frontside to its backside to establish conduction paths to at least some of the programmable elements from the backside. A programming stimulus is applied to at least some of the vias from the backside to program at least some of the frontside programmable elements.

Systems and methods are disclosed to automatically synthesize a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks to implement one or more instructions; determining an instruction execution sequence based on the code profile and reassigning the instruction sequence to spread operation to different blocks on the IC to reduce hot spots; and synthesizing the generated processor chip specification into a computer readable description of the custom integrated circuit for semiconductor fabrication.

Systems and methods are disclosed to automatically determine an optimal number format representation for a model or code to be implemented in a custom integrated circuit (IC) by determining a ratio of dynamic range to static range in the model or code, and selecting a floating point or a fixed point number representation based on the ratio; determining the optimal number representation format based on a cost function that includes hardware area and power cost associated with a predetermined bit precision arithmetic; automatically generating a processor architecture customized to the optimal number representation format; and synthesizing the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

Systems and techniques for facilitating layout of an integrated circuit (IC) design are described. A distinct color pattern can be assigned to a set of shapes in a layout of the IC design that correspond to a net. Next, the layout of the IC design can be displayed in a graphical user interface (GUI) of the IC design tool. Some embodiments can move a diffusion region of a multigate device with respect to the location of the device contacts so that the diffusion region is aligned with respect to a set of fin tracks, wherein each fin of each multigate device is located on a fin track.

A system, method, computer program product for verification and equivalence checking. In one approach, the system, method, and computer program product analyzes the switching paths in a manner consistent with circuit functionality to provide a complete application which can verify the complex characteristics in the circuits to the accurate RTL model function, including FPGA, ROM Arrays, RAM circuits, and other custom integrated circuit designs.

A fixed logic integrated circuit is disclosed. The integrated circuit includes a unique code generator (3) configured to generate a code (4) having a value inherently unique to the integrated circuit, a registration pattern generator configured to generate a registration pattern (6) based on the unique code (4) (5). The integrated circuit is configured to transmit a registration pattern (6) to an external registration device (2) and to receive enabling data (7) from the external registration device. Optionally, the integrated circuit may comprise a memory (8) for storing remotely generated enabling data (7). The integrated circuit includes: a configuration file generator (9) configured to generate configuration data (10) using remotely generated enablement data (7) and a unique code (4); and a feature activation module (11) configured to To activate and / or deactivate features (13) of the integrated circuit and / or to customize the integrated circuit according to the configuration data (10).

Systems and methods are provided that may be implemented to produce customized integrated circuit (IC) device parts together from a common base IC device part that is customized with settings or code to build different unique IC device parts for different purposes that are processed and output together from the manufacturing process. Different individual devices of the common base part may be customized (e.g., programmed) with different settings and / or code to build respective uniquely configured parts for different purposes, e.g., such as according to different respective part orders.

The invention discloses a method of structuring a multiport asynchronous storage module and relates to buffer storage and interchange of multichannel parallel data in the process of data interchange and processing. The method of structuring the multiport asynchronous storage module aims at solving the problem that in the process of design of a current semi-custom integrated circuit, a used storer of a technological library just has two types of single ports or double ports and can not meet certain situations of high data throughput rates. An addressing manner of address decoding control partitioning reading and writing is adopted by a plurality of double-port type storers in the technological library to structure the multiport asynchronous storage module, so that the aim that a simple port storage module is structured to the multiport storage module is achieved, and the requirement for the high data throughput rates is reached. The method of structuring the multiport asynchronous storage module has the advantages of flexibly expanding capacity and available access ports of the storer according to design requirements, reducing design difficulty, and shortening development time. Relative to a full-custom multiport storer, the method of structuring the multiport asynchronous storage module has the advantages of being good in flexible performance, high in reliability, small in design risk and the like.

Eight Applications Specific Integrated Circuits (ASICs) for use in stand-alone end products and other devices requiring a 24 hour memory. They have a real-time clock as well as memory that stores On and Off Switch closures with the ability to repeat them. They also have power management to allow them to operate by receiving their power through the load they are switching. They also have LED drivers to indicate the function being performed. They can store a resolution of two minute or one minute intervals of On and Off Switch closures per 24 hour period depending upon the amount memory integrated into the ASIC. Only a few external components are required to create end products and / or utilize these ASICs in another product.