39 results about "Custom integrated circuits" patented technology

A method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox allows a reduction in the number of fuses required to repair or customize an integrated circuit and allows fuses to be grouped outside of the macros repaired by the fuses. The remote location of fuses allows flexibility in the placement of macros having redundant repair capability, as well as a preferable grouping of fuses for both programming convenience and circuit layout facilitation. The fuses are arranged in rows and columns and represent control words and run-length compressed data to provide a greater quantity of repair points per fuse. The data can be loaded serially into shift registers and shifted to the macro locations to control the selection of redundant circuits to repair integrated circuits having defects or to customize logic.

A customizing method includes steps which consist in: a) determining on the basis of a circuit model, a set of vectors each corresponding to a theoretical operating time of the circuit when a predetermined sequence of tests is applied, the coefficients of each vector representing the state of a common set of elements of the circuit among which the element to be customized (12); b) defining on the basis of a comparison of vectors, a composite of logic operators applied on the vectors and enabling to extract the coefficient corresponding to the element to be customized (30); c) producing images of the operating circuit at times corresponding to the vectors whereon is applied the composite of logic operators (32); and d) graphically combining the images produced in accordance with a composite of graphic operators corresponding to the composite of logic operators (36).

The invention discloses a method for realizing a reconfigurable accelerator customized for a program. The reconfigurable accelerator customized for the program accelerates the program on an FPGA by arranging the FPGA for the prior general-purpose computer system. The method has a main function of analyzing the program, uses functions to calculate information for the runtime of a granularity sampling program, acquires computing-intensive hot spot functions in the program, realizes the hot spot functions as the reconfigurable accelerator on the FPGA, and modifies call of the hot spot functions in the program into call of the corresponding reconfigurable accelerator to accelerate execution of the hot spot functions. The method uses the reconfigurable accelerator to realize the hot spot functions of the program, improves the total speed-up ratio of the program, uses the FPGA to realize the reconfigurable accelerator, achieves the performance of an approximately applied custom integrated circuit, and simultaneously maintains the flexibility of a general-purpose processor.

A semiconductor device includes a mother chip having a standard integrated circuit and electrodes pads, and an option chip having a custom integrated circuit, the option chip being provided over a part of the mother chip via connectors.

A system for performing device-specific testing and acquiring parametric data on custom integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The testing system includes a device test structure integrated into unused backfill space in an ASIC design which tests a set of dummy devices that are identical to some of those of the ASIC. The device test structure includes control logic for designating the type of test and which device types to activate (e.g. pFETs or nFETs), a protection circuit for protecting the SPM when the test is inactive, an isolation circuit for isolating the devices under test (DUT) from any leakage current during test, and a decode circuit for providing test input (e.g. voltages) to the DUT. By controlling which devices to test and the voltage conditions of those devices, the system calculates the relative product yield and health of the line on a die by die basis.

A method for laying out custom integrated circuits includes the steps of preliminarily laying out a custom integrated circuit using a plurality of libraried standardized programmed cells (p-cells). Buildcode representations are then assigned for each of a plurality of circuit components and features thereof to realize customization of at least a portion of the plurality of p-cells. A final layout of the custom integrated circuit is then generated using the buildcode representations.

The invention discloses a high-speed LVDS serial synchronization communication controller. The high-speed LVDS serial synchronization communication controller comprises a microcontroller interface module (1), a work register array module (2), a receiving time sequence generator module (3) and a sending time sequence generator module (4). The high-speed LVDS serial synchronization communication controller can be matched with a serializer MAX9217, a deserializer MAX9218 and other customized integrated circuits of a Canada MAXIM company to form a full duplex and high speed LVDS synchronization serial communication interface. A control order, parameters and data given by an X80 series microcontroller can be received, the information exchanging process is controlled, and the working state of the high-speed LVDS serial synchronization communication controller is fed back to an X86 series microcontroller. When one frame of data are received or sent, an interrupt request signal of the X86 series microcontroller can be automatically produced. A user system can be assisted to achieve an information exchange protocol defined by a user, reliable high-speed, serial and synchronous full duplex data exchange between two electronic information systems connected through an LVDS signal line is achieved.

Systems and methods are disclosed to automatically generate a processor architecture for a custom integrated circuit (IC) described by a computer readable code. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters until, all timing and hardware constraints expressed as a cost function are met; and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.

The invention discloses a method of structuring a multiport asynchronous storage module and relates to buffer storage and interchange of multichannel parallel data in the process of data interchange and processing. The method of structuring the multiport asynchronous storage module aims at solving the problem that in the process of design of a current semi-custom integrated circuit, a used storer of a technological library just has two types of single ports or double ports and can not meet certain situations of high data throughput rates. An addressing manner of address decoding control partitioning reading and writing is adopted by a plurality of double-port type storers in the technological library to structure the multiport asynchronous storage module, so that the aim that a simple port storage module is structured to the multiport storage module is achieved, and the requirement for the high data throughput rates is reached. The method of structuring the multiport asynchronous storage module has the advantages of flexibly expanding capacity and available access ports of the storer according to design requirements, reducing design difficulty, and shortening development time. Relative to a full-custom multiport storer, the method of structuring the multiport asynchronous storage module has the advantages of being good in flexible performance, high in reliability, small in design risk and the like.

Systems and methods are disclosed to automatically generate a custom integrated circuit (IC) design by receiving a specification of the custom IC including computer readable code to be executed by the custom IC; generating an abstraction of the IC as a system, processor architecture and micro-architecture (SAMA) representation; providing the SAMA representation to a data model having at least an architecture optimization view, a physical design view, and a software tool view; optimizing the processor architecture by iteratively updating the SAMA representation and the data model to automatically generate a processor architecture uniquely customized to the computer readable code which satisfies one or more constraints; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. The foregoing can be done with no or minimal human involvement.

Systems and methods are disclosed to automatically synthesize a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit, encoding architecture level knowledge in a data model to generate and pass new constraints for physical synthesis of a chip specification uniquely customized to the computer readable code, receiving a look-ahead cost function during architecture optimization consistent with cost observed later in the flow after detailed physical synthesis is performed, wherein the look-ahead cost function is generated from a prior iteration and supplied to a subsequent iteration through the data model, and automatically translating information available at one optimization point into a constraint for another optimization point invoked at a different place in the design flow using the data model.

Comparisons between two nucleotide sequences can be performed by customized integrated circuity that can implement a Smith Waterman analysis in a reduced memory footprint, storing and referencing onlyindividual portions, or subsections, of a two-dimensional matrix that is representative of the comparison between the two nucleotide sequences. As the backtracking proceeds, backtracking metadata corresponding to a cell from a subsection that is not currently retained in memory can be required. Such a subsection can be regenerated from previously generated scores associated with checkpoint cellsof the two-dimensional matrix that comprise two edges of the subsection being regenerated. Moreover, to further reduce memory consumption, the backtracking metadata stored for each cell can comprise four binary digits: two indicative of a directional assignment, one indicative of whether the corresponding cell is part of a deletion stretching across multiple contiguous cells, and one analogously indicative of insertions stretching across multiple contiguous cells.

This patent outlines the design of a family of Applications Specific Integrated Circuits (ASICs) for specific use in stand-alone end products and other devices needing 24 hour timer functions. These ASICs have a built-in real-time clock as well as a memory storage function remembering On and Off switch activity with the ability to repeat it. The ASICs have LED drivers indicating the function being performed. The power-on indicator also doubles as night light feature.

These ASICs can store two minute or one minute intervals of power switch changes per day depending upon the amount of shift register memory placed in the ASICs. The memory function doubles as a static shift register for storage as well as providing a large portion of the real time 24 hour clock. These ASICs fully integrate most of the electronics required for stand-alone memory timers. Only a few additional components are required to fully create products using these ASICs.

A bezel of a display includes source lines with a same length, gate in panel (GIP) lines, and at least two customized integrated circuit (IC) chips arranged along a straight line in a lateral direction. Each of the customized IC chips is coupled to at least one of the source lines or the GIP lines. Circuit layouts on the customized IC chips are, together, equivalent to a circuit layout on a standard IC chip. A sum of widths of the customized IC chips in the lateral direction is greater than a width of the standard IC chip.