Integrated data model based framework for driving design convergence from architecture optimization to physical design closure

A data model, physical technology, applied in the framework field based on integrated data model used to drive design convergence from architectural optimization to physical design closure, can solve problems such as discontinuity of basic data model, and achieve the effect of alleviating the problem

Inactive Publication Date: 2013-08-21
ALGOTOCHIP
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Thus, there is a discontinuit

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  • Integrated data model based framework for driving design convergence from architecture optimization to physical design closure
  • Integrated data model based framework for driving design convergence from architecture optimization to physical design closure
  • Integrated data model based framework for driving design convergence from architecture optimization to physical design closure

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[0022] now turn to reference figure 2 , a framework with an Integrated Data Model (IDM) 270 is used according to one aspect of the invention. exist figure 2 , the architectural / microarchitectural design optimization engine 200 communicates with an architectural optimization (AO) adapter 230 . Additionally, instruction scheduler 210 may be in communication with instruction scheduler adapter 240 . Likewise, physical design optimization engine 220 communicates with physical design adapter 250 . Adapters 230 , 240 , and 250 communicate via sideband communication channel 260 , which communicates with integrated data model 270 .

[0023] The sideband communication channel 260 enables various optimization processes to communicate contextual information to a communication medium where such information is passively maintained continuously throughout the process. In the context of an EDA tool-based SoC design flow, this channel 260 is implemented using non-intrusive significant se...

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Abstract

Systems and methods are disclosed to automatically synthesize a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit, encoding architecture level knowledge in a data model to generate and pass new constraints for physical synthesis of a chip specification uniquely customized to the computer readable code, receiving a look-ahead cost function during architecture optimization consistent with cost observed later in the flow after detailed physical synthesis is performed, wherein the look-ahead cost function is generated from a prior iteration and supplied to a subsequent iteration through the data model, and automatically translating information available at one optimization point into a constraint for another optimization point invoked at a different place in the design flow using the data model.

Description

technical field [0001] The invention relates to a frame used for EDA design convergence. Background technique [0002] figure 1 A high-level view showing a typical SoC design flow. In conventional system-on-chip (SoC) processing, the design specification 1 is processed using an architectural / micro-architectural design optimization block 40 . The result of this block 40 is the behavior register transfer language (RTL) 150 received by the netlist synthesis block 50 . A gating level netlist 160 is generated, which physical synthesis block 60 can use to generate a full chip layout. The layout can be analyzed by the full chip analysis block 70 . The delay dependency updates may be provided as feedback to the architectural / micro-architectural design optimization block 40 . Additionally, critical delay information may be provided to netlist synthesis module 50 . Typically, this process requires implementing the complete design within a number of specialized optimization modul...

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/30G06F2111/04G06F2117/08
Inventor 阿南斯·朵巴皮尔斯·吴萨蒂许·帕德马纳班
Owner ALGOTOCHIP
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