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System, architecture and micro-architecture (sama) representation of an integrated circuit

An integrated circuit and processor architecture technology, applied in computer-aided design, software simulation/interpretation/simulation, special data processing applications, etc. The effect of mitigating the problem

Inactive Publication Date: 2013-05-08
ALGOTOCHIP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] However, RTL is still a low-level description of hardware
Thus, it may be difficult to analyze and subsequently optimize the design using RTL

Method used

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  • System, architecture and micro-architecture (sama) representation of an integrated circuit
  • System, architecture and micro-architecture (sama) representation of an integrated circuit
  • System, architecture and micro-architecture (sama) representation of an integrated circuit

Examples

Experimental program
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Embodiment Construction

[0043] figure 1 An example workflow system for automated fabrication of ASICs from application code or algorithms is shown. First, the user generates application code or algorithms (110). This code is then provided to the architecture optimizer 112 . Architecture optimizer 112 generates an intermediate hardware representation tailored to the application code, referred to as the System, Architecture and Microarchitecture (SAMA) representation 120 which is an abstract unified representation of the ASIC. SAMA 120 is a high-level lightweight abstraction module that enables architecture optimizer 112 to optimize and generate new architectures described in SAMA 120 . SAMA 120 provides information to Data Model (DM) 130 which is an extended unified functional and physical model of the ASIC. The DM 130 receives, for example, physical raw information of ASICs such as adders and multipliers. DM 130 provides data to a tool generator 134 which drives a set of tools 136 such as compile...

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Abstract

Systems and methods are disclosed to automatically generate a custom integrated circuit (IC) design by receiving a specification of the custom IC including computer readable code to be executed by the custom IC; generating an abstraction of the IC as a system, processor architecture and micro-architecture (SAMA) representation; providing the SAMA representation to a data model having at least an architecture optimization view, a physical design view, and a software tool view; optimizing the processor architecture by iteratively updating the SAMA representation and the data model to automatically generate a processor architecture uniquely customized to the computer readable code which satisfies one or more constraints; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. The foregoing can be done with no or minimal human involvement.

Description

[0001] Cross References to Related Applications [0002] This application is related to commonly owned and concurrently filed applications No. 12 / 835,603 entitled "AUTOMATIC OPTIMAL INTEGRATED CIRCUIT GENERATOR FROM ALGORITHMS AND SPECIFICATION", application No. 12 entitled "AUTOMATIC OPTIMAL INTEGRATED CIRCUIT GENERATOR FROM ALGORITHMS AND SPECIFICATION" / 835,621, Application No. 12 / 835,628 titled "APPLICATION DRIVEN POWER GATING", Application No. 12 / 835,631 titled "SYSTEM, ARCHITECTURE AND MICRO-ARCHITECTURE (SAMA) REPRESENTATION OF AN INTEGRATED CIRCUIT" application and application number 12 / 835,640, titled "ARCHITECTURAL LEVEL POWER-AWARE OPTIMIZATION AND RISK MITIGATION," the contents of which applications are hereby incorporated by reference. technical field [0003] The present invention relates to systems and methods for intermediate representation of custom integrated circuits (ICs) or application specific integrated circuits (ASICs). Background technique [0004] ...

Claims

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Application Information

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IPC IPC(8): G06F9/455
CPCG06F17/505G06F9/44G06F30/327G06F9/455
Inventor 皮尔斯·吴瑟雷许·凯迪耶拉萨蒂许·帕德马纳班
Owner ALGOTOCHIP
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