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Architectural level power-ware optimization and risk mitigation

A technology of power and processor architecture, applied in program control devices, software simulation/interpretation/simulation, CAD circuit design, etc., can solve problems such as long processing, costing millions of dollars, etc. Avoiding, high-performance effects

Inactive Publication Date: 2013-09-04
ALGOTOCHIP
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This process can be lengthy and can cost millions of dollars depending on the complexity of the design

Method used

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  • Architectural level power-ware optimization and risk mitigation
  • Architectural level power-ware optimization and risk mitigation
  • Architectural level power-ware optimization and risk mitigation

Examples

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Embodiment Construction

[0030] figure 1 An example system for automatically generating custom ICs is shown. figure 1 The system supports the automatic generation of the best customized integrated circuit solution for the selected target application. The specification of the target application program is usually realized by using a high-level language such as C, Matlab, SystemC, Fortran, Ada, or any other language to express an algorithm as a computer-readable code. The specification includes a description of the target application and also includes one or more constraints such as expected cost, area, power, speed, performance, and other attributes of the hardware solution. In order to assist the physical synthesis, the system encodes the "sideband" information into a netlist file, and can obtain design constraints (physical and timing) that are more effective in guiding the physical synthesis than the original user constraints alone. In certain embodiments, these constraints are "implied" through the ...

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Abstract

Systems and methods are disclosed to automatically synthesize a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks to implement one or more instructions; determining an instruction execution sequence based on the code profile and reassigning the instruction sequence to spread operation to different blocks on the IC to reduce hot spots; and synthesizing the generated processor chip specification into a computer readable description of the custom integrated circuit for semiconductor fabrication.

Description

[0001] Cross references to related applications [0002] This application relates to the jointly owned and concurrently filed application number 12 / 835,603 with the title "AUTOMATIC OPTIMAL INTEGRATED CIRCUIT GENERATOR FROM ALGORITHMS AND SPECIFICATION" and the application number 12 with the title "AUTOMATIC OPTIMAL INTEGRATED CIRCUIT GENERATOR FROM ALGORITHMS AND SPECIFICATION" / 835,621 application, application titled "APPLICATION DRIVEN POWER GATING" application number 12 / 835,628, application titled "SYSTEM,ARCHITECTURE AND MICRO-ARCHITECTURE(SAMA) REPRESENTATION OF AN INTEGRATED CIRCUIT" application number 12 / 835,631 The application and the application titled "ARCHITECTURAL LEVEL POWER-AWARE OPTIMIZATION AND RISK MITIGATION" application number 12 / 835,640, the contents of these applications are incorporated herein by reference. Technical field [0003] The invention relates to a method and equipment for optimization and risk reduction of architecture-level power monitoring. Back...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/455
CPCG06F30/30G06F9/455G06F30/39G06F30/3308G06F30/337
Inventor 阿南斯·朵巴皮尔斯·吴盖瑞·欧布拉克瑟雷许·凯迪耶拉萨蒂许·帕德马纳班
Owner ALGOTOCHIP
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