7 results about "SystemC" patented technology

This invention discloses a virtual prototype platform based on a convolutional neural network microprocessor. Based on the existing RISC-V virtual prototype platform, this platform has the following features: First, using inline assembly, vector extensions and matrix operation instruction extensions are added to the compiler tool. This allows the compiler tool to recognize these instructions during compilation and successfully compile them into corresponding machine code for execution by the CPU hardware model. Second, by modifying the pipeline of the RISC-V virtual prototype processor hardware model, two SystemC modules, a vector loading module and a matrix operation module, are added to the pipeline, thereby enabling the construction of a virtual prototype platform for the CNN microprocessor. This invention can solve problems such as achieving hardware-software collaborative design during the design of CNN microprocessors.

The present invention discloses a simulation calculation method, device, equipment, product and medium for a simulation system, relating to the field of simulation technology. The method is applied to a downlink port device and includes: allocating a current parallel computing task to a target simulation thread; using the operating system thread corresponding to the target simulation thread to execute the current parallel computing task, and blocking the operation of the target simulation thread in a target blocking manner according to the preset simulation time of the current parallel computing task; if the blocking duration of the target simulation thread reaches the preset simulation time and the operating system thread has completed the current parallel computing task, using other simulation threads to process the corresponding simulation computing tasks; The present invention can, on the basis of retaining the SystemC standard, perform parallel construction on some key areas of performance consumption, improve the operation efficiency of the entire simulation system, and is applicable to simulation models with loose clocks, having better application universality.

The invention discloses a simulation workflow timeout monitoring method and device, equipment and a medium, relates to the technical field of computers, is applied to a SystemC timing thread, and comprises the following steps: after a SystemC working thread sets an expected timeout duration of a target simulation workflow, creating an operating system timing thread according to a flow start signal sent by the working thread; setting the timing duration of the timing thread of the operating system based on the expected timeout duration; judging whether the target simulation workflow is overtime or not according to the receiving sequence of the first mark updating notice and the second mark updating notice, and executing corresponding processing operation based on a judgment result; the first mark update notification is an update notification of a completion mark corresponding to timing completed by the timing thread of the operating system based on the timing duration; the second mark update notification is an update notification of a corresponding end mark when the SystemC working thread finishes executing the target simulation working process. According to the invention, high-precision physical clock timing control can be carried out.

The application provides a SystemC-based virtual model generation method, system, medium and equipment, the method comprises the following steps: receiving the name of a hardware module input by a user, and executing a first script based on the hardware module to generate a model directory structure; receiving a register description file input by the user, and parsing the register description file through a second script to generate a SystemC-based register model in the model directory structure; executing a third script to generate a source code file of a virtual model of the hardware module in the model directory structure based on the register model; receiving custom function information for the hardware module added by the user on the source code file to obtain a virtual model implementing the custom function. The application greatly shortens the development time of the virtual model of the hardware module.

The invention discloses a method, a medium and a product for SystemC system performance analysis. The method comprises the following steps: defining a group of transaction marking API (Application Program Interface) functions, including a starting function and an ending function; calling a starting function at the starting point of the transaction in the SystemC system, and calling an ending function at the ending point of the transaction; in the simulation execution process of the SystemC system, in response to calling of a starting function and an ending function, transaction information associated with a transaction is captured and recorded, and the transaction information comprises a starting timestamp, an ending timestamp, a grouping identifier and a transaction name of the transaction; grouping the transactions according to the grouping identifiers of the transactions to generate one or more transaction groups; and generating an independent timeline track for each transaction group, and drawing graphic elements representing the duration of the transaction on the timeline track according to the start and end times of each transaction to generate a grouped transaction active timeline graph.

The invention belongs to the technical field of deep learning accelerators, and particularly relates to a design method of a deep learning accelerator vector processing unit based on SystemC. Comprising the following steps: constructing a uniform vector processing unit by using a SystemC transaction-level model to replace pooling and normalization modules accelerated by a traditional deep learning algorithm; the interior of the vector processing unit comprises a reconfigurable dynamic configuration so as to realize various data processing modes of a pooling operator, a normalization operator, a pixel summation operator and an up-sampling operator; the enhanced multi-dimensional DMA engine is used for carrying out directional data slicing and moving on the input three-dimensional data cube in different dimensions according to the configuration parameters; according to the method, the problems of hardware islands, low resource utilization rate, inflexible data transfer and the like existing in the original discrete design are solved, and the universality, the energy efficiency ratio and the execution efficiency of the accelerator are remarkably improved.

The invention provides a multi-chip simulation method, system and device and a storage medium, a chip in multi-chip simulation comprises a CPU and a plurality of CGRA assemblies, each CGRA assembly comprises a CGRA front-end interface and a rear-end CGRA simulator, the rear-end CGRA simulator based on SystemC is packaged into a dynamic link library capable of being recognized by SST, the CGRA front-end interface is used as connection to interact with SST during operation, and the SST is used as a dynamic link library capable of being recognized by SST. And the compatibility problem of the SystemC and the SST framework is solved. In an SST simulation framework, a communication link of a CPU and a CGRA assembly is established, an application program is operated, a CGRA task needing to be executed and a data packet needed for operating the CGRA task are determined, the data packet is transmitted to the corresponding CGRA assembly through the communication link, the data packet is received through a CGRA front-end interface of the CGRA assembly, a rear-end CGRA simulator is driven to perform task operation, and multi-core simulation is achieved.