Topological structure analyzing method and state machine model extracting method of time sequence circuit

Abstract

The invention relates to a topological structure analyzing method and a state machine model extracting method of a time sequence circuit. The method is applicable to the time sequence circuit described according to SystemC and including a trigger and an elementary gate, wherein the trigger and the elementary gate are described by SystemC. Circuit information reflects a topological structure of a circuit and comprises trigger number and port information thereof, gate device type and port information thereof as well as primary input end number and information of a logic device connected with each lead. The method mainly comprises the following steps of: extracting circuit topological structure information; constructing a Boolean function of the circuit; showing the Boolean function of state transfer by using a binary decision diagram; initializing a time sequence circuit; and calculating the Boolean function of state transfer by using a constraint solver. According to the invention, by using a gate-level time sequence circuit state machine model extracting algorithm, the time sequence circuit state machine model can be very well obtained without need of applying any motivation to the design so that the complicatedness of realization is avoided.

Description

technical field [0001] The invention relates to the technical field of SystemC formal verification, in particular to a SystemC-based sequential circuit topology analysis method and a SystemC-based sequential circuit state machine model extraction method. Background technique [0002] At present, the chip design industry is facing a series of challenges. With the rapid development of semiconductor technology, SoC (System-on-Chip, system on chip or system chip) has become the development direction of today's integrated circuit design, and the performance of SoC is getting stronger and stronger. , the scale is getting bigger and bigger. The scale of SoC chips is generally much larger than that of ordinary ASICs. At the same time, due to the design difficulties brought by deep submicron technology, the complexity of SoC design is greatly increased. In SoC design, simulation and verification are the most complex and time-consuming links in the SoC design process, accounting for ...

AI Technical Summary

Problems solved by technology

Applying formal verification techniques to SystemC designs will be a challenge because SystemC is an object-oriented design language and because of SystemC's complex event-driven simulation semantics

[0005] Most of the traditional verification methods use dynamic simulation. One of the main disadvantages of dynamic simulation is that in a time-limited simulation process, only the typical operating characteristics of the chip can be verified.

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