35results about How to "Short interconnect" patented technology

An area efficient stacked TCAM cell for fully parallel search. The TCAM cell includes a top half circuit portion interconnected with a replicated bottom half circuit portion such that there is a shared match line between each of the half circuit portions. Each TCAM cell includes a pair of memory elements that is connected to a pair of associated compare circuits such that the interconnections between the memory elements and the compare circuits are substantially vertical in active MOS layers and substantially horizontal in metal layers. The memory elements and the compare circuits are connected such that they facilitate shorter interconnections and sharing of terminals at the boundary of adjacent cells. The resulting stacked TCAM cell provides shorter match lines, shared bit lines, and reduced silicon area to facilitate improved routing and performance.

The invention discloses a 3D strained NMOS integrated device and a manufacturing method thereof, relates to the technical field of microelectronics, and mainly solves the problem of low speed of the existing 3D integrated circuit. The proposal is that an SSOI substrate and an SGOI substrate are employed to construct two active layers of a new 3D integrated device; wherein, the lower active layer is the SSOI substrate and is made into strained Si NMOSFET with a poly-SiGe gate by utilizing the characteristic of high electron mobility of a strained Si material in the SSOI substrate; the upper active layer is the SGOI substrate on which a layer of strained Si grows and is made into strained Si surface channel NMOSFET with the poly-SiGe gate; the lower active layer and the upper active layer are connected by an interconnection line to form the 3D strained NMOS integrated device with a conducting channel of 65nm to 130nm. Compared with the existing 3D integrated devices, the 3D strained NMOS integrated device manufactured by the manufacturing method has the advantages of high speed and good performance, and can be applied to manufacturing large-scale and high-speed 3D CMOS integrated circuits.

The invention discloses a method of serial communication, wherein, master equipment is connected with a plurality of slave equipments; the master equipment provides a communication clock signal (CLK) to the slave equipment by a clock signal wire, notifies the slave equipment to start reading / writing operation by a synchronous signal (SYN), and transmits a slave equipment address or a register address to the slave equipment by a downstream data signal (CMD); and the master equipment transmits downstream data to the slave equipment by the downstream data signal (CMD), or the slave equipmen transmits upstream data to the master equipment by an upstream data signal (DAT). The method of serial communication comprises a serial communication method of the master equipment, a serial communication method of the slave equipment and a serial communication method for interaction of the master equipment and the slave equipment. The invention also discloses the master equipment and the slave equipment. The proposal of the invention has the advantages of easy realization, pin resource conservation and cost reduction.

The invention discloses a 3D quantum well NMOS integrated device and a manufacturing method thereof, relates to the technical field of microelectronics, and mainly solves the problem of low speed of the existing 3D integrated circuits. The proposal is that an SSOI substrate and an SGOI substrate are respectively employed to construct two active layers of a new 3D integrated device; wherein, the lower active layer is the SSOI substrate and is made into strained Si NMOSFET by utilizing the characteristic of high electron mobility of a strained Si material in the SSOI substrate; the upper activelayer is the SGOI substrate on which a strained Si / relaxed SiGe double-layer structure grows and is made into strained Si quantum well channel NMOSFET; the lower active layer and the upper active layer are connected by an interconnection line to form the 3D quantum well NMOS integrated device with a conducting channel of 65nm to 130nm. Compared with the existing 3D integrated devices, the 3D quantum well NMOS integrated device manufactured by the manufacturing method has the advantages of high speed and good performance, and can be applied to manufacturing large-scale and high-speed 3D CMOS integrated circuits.

The invention relates to a configurable three-dimensional microwave filter based on coaxial silicon through holes. The configurable three-dimensional microwave filter comprises a ground layer, a firstinterconnect layer, a silicon through hole capacitor layer and a second interconnect layer in order from top to bottom, wherein a plurality of first connecting members are disposed on the first interconnect layer; a plurality of second connecting members are disposed on the second interconnect layer; the ground layer includes a ground lead-out terminal which is selectively grounded; the silicon through hole capacitor layer includes a substrate and a plurality of silicon through hole structures penetrating through the substrate; the plurality of silicon through hole structures are successivelyconnected end to end through the plurality of first connecting members and the plurality of second connecting members to form a three-dimensional spiral inductor. The configurable three-dimensional microwave filter is compact in structure, high in utilization efficiency, low in chip area, and integrated, avoids introduction of additional loss, is short in interconnect line, low in parasitic parameter and low in off-chip coupling.

The invention discloses a multi-core storage system emulator based on on-chip network interconnection, which is characterized in that the emulator uses the core of SystemC as the driving core of the entire emulator, and includes a first-level cache for simulating each processor core The caching module, the routing module for simulating the L2 cache of each processor core and the QEMU module for providing functional simulation; several routing modules are connected to the on-chip network formed by the L2 cache shared by the simulation processor cores, Each routing module is provided with a set of signal lines connected to the cache module; the routing module distributes the pkt message delivered by the cache module or the routing module to another cache module or another routing module. The emulator can be used to develop the system software of the target system, so that the software and hardware can be developed simultaneously, and the system development speed can be accelerated.

The invention discloses a silicon-based uniwafer photoelectricity integrated receiving chip for plastic optical fiber communication, and relates to a silicon-based uniwafer photoelectricity integrated circuit. The chip is a uniwafer photoelectricity integrated receiving chip with the wavelength of 650 + / - 17.8nm for the plastic optical fiber communication; and a photoelectricity probe chip and a preposed amplifying integrated circuit chip in a light receiving module with the wavelength of 650 + / - 17.8nm for the conventional plastic optical fiber communication can be replaced by the chip, so that the uniwafer photoelectricity integration of the photoelectricity probe and the preposed amplifying integrated circuit with the wavelength of 650 + / - 17.8nm is realized; a requirement on 100Mbps transmission velocity for the plastic optical communication can be met; and the chip can be used for the light receiving end with the wavelength of 650 + / - 17.8nm for the plastic optical fiber communication; and moreover, the chip can be prepared by a 0.5-micron standard binary-coded decimal (BCD).