2results about How to "Short interconnect" patented technology

The invention provides an interrupt management method and device for a computer processor, and the method comprises the steps: setting an interrupt latch management module, setting M groups of interrupt functions in the interrupt latch management module, enabling each group of interrupt functions to correspond to N interrupt sources, enabling each interrupt source to correspond to one register, when the interrupt function receives an interrupt pulse sent by an interrupt source, the interrupt state of the interrupt source is stored in a register corresponding to the interrupt source; and allocating an independent weight configuration to each group of interrupt functions, performing weighted polling arbitration on all registers of the M groups of interrupt functions according to corresponding weights, selecting polled effective registers, generating corresponding interrupt information, and outputting the interrupt information to a bus for reporting. Compared with the prior art, the interrupt management structure is simple and flexible, the resource consumption is low, and the interrupt state can be reported in time according to needs.

The application provides an interrupt management method and device of a computer processor, and the interrupt management method comprises the following steps: setting an interrupt latch management module, setting M groups of interrupt functions in the interrupt latch management module, each group of interrupt functions corresponding to N interrupt sources, each interrupt source corresponding to a register, and the interrupt function storing the interrupt state of the interrupt source in the register corresponding to the interrupt source when receiving the interrupt pulse sent by the interrupt source; allocating an independent weight configuration to each group of interrupt functions, performing weighted round-robin arbitration on all registers of the M groups of interrupt functions according to the corresponding weight, selecting the effective register polled, generating the corresponding interrupt information and outputting the interrupt information to a bus for reporting. Compared with the prior art, the interrupt management structure of the application is simple and flexible, the resource consumption is small, and the interrupt state can be reported in time according to the needs.