35results about How to "Short interconnect" patented technology

The invention discloses a 3D system integration structure, comprising: an adapter board; A first silicon through hole arranged on the front face of the adapter board; A second silicon through hole arranged on the front face of the adapter board; A cavity arranged on the back surface of the adapter plate; A first relayout wiring layer and a pad arranged on a bottom surface of the cavity, the firstrelayout wiring layer and the pad being electrically connected with the first silicon via; A first chip disposed within the cavity, the first chip electrically connected to the first relayout wiring layer and the pad; A plastic filling layer arranged around the first chip and having a gap between the bottom and the adapter board; A second chip arranged on the back surface of the adapter board, thesecond chip being electrically connected to the second silicon through hole; A second relayout wiring layer disposed on a front face of the adapter board; And a welding structure provided on the front face of the adapter plate, the welding structure being electrically connected to the second relayout wiring layer.

The invention relates to an optical receiving assembly for hundred trillion-grade 850nm optical communication and a preparation method thereof, and provides an optical receiving assembly for hundred trillion-grade 850nm optical communication, which is compatible with a commercial CMOS process and can replace the hybrid integration in the traditional 850nm optical transceiver and meet the transmission requirement, and a preparation method thereof. The optical receiving assembly is provided with a 850nm optoelectronic single integrated receiving chip, a pipe seat, a pipe cap, a pipe pin and an adapter, wherein the chip is provided with a prepositive amplifying circuit and an optoelectronic detector, and the prepositive amplifying circuit is provided with two mutual resistance type amplifying circuits, a three-grade differential amplifier, an output buffer circuit and a direct current negative feedback circuit. The optoelectronic detector is provided with a low doped P-shaped silicon substrate, a P pit, an N-shaped heavy doping silicon layer, a field oxide layer, an aluminum layer, three SiO2 insulating medium layers and a Si3N4 surface passivating layer from bottom to top in the longitudinal direction. The chip is attached to the pipe seat by a CMOS process; a welding disk of the chip is bonded with the pipe pin by a gold thread; and the pipe cap is covered to be encapsulated with the adapter according to the same shaft.

This invention discloses a TD-SCDMA mobile phone circuit board realizing effective and integrating distribution. It includes LCD screen module, the antenna, the digital baseband part, the radio frequency and stimulant baseband part. The relating circuit board has the upper and the lower layer, the lower layer includes the antenna on the upper part, and the antenna is internally set in the mobile phone, the middle part is the radio frequency part and the lower part is the stimulant baseband part. The upper layer mainly includes the LCD screen module of the upper part and the digital baseband part of the bottom. This invention realizes the effective distribution of TD-SCDMA mobile phone circuit board. In order to avoid the interfere between the modules, it uses the shielding can effectively isolate the radio frequency module, the stimulant baseband part and the digital baseband part and realizes the minimization of the product.

The invention provides a monolithic integration method for a grating optical modulator and an active matrix drive circuit, which is combined with the processing technique of monolithic integration of an MEMS device and a CMOS circuit, utilizes the CMOS circuit to process the active matrix drive circuit at first and then utilizes the low-temperature micromechanical manufacturing technique to obtain the MEMS grating optical modulator, so as to realize monolithic integration of the MEMS grating optical modulator which is formed by upper movable gratings supported on lower electrodes and the lower active matrix drive circuit. The grating optical modulator processed by the technique can project and display with high definition and high resolution.

An area efficient stacked TCAM cell for fully parallel search. The TCAM cell includes a top half circuit portion interconnected with a replicated bottom half circuit portion such that there is a shared match line between each of the half circuit portions. Each TCAM cell includes a pair of memory elements that is connected to a pair of associated compare circuits such that the interconnections between the memory elements and the compare circuits are substantially vertical in active MOS layers and substantially horizontal in metal layers. The memory elements and the compare circuits are connected such that they facilitate shorter interconnections and sharing of terminals at the boundary of adjacent cells. The resulting stacked TCAM cell provides shorter match lines, shared bit lines, and reduced silicon area to facilitate improved routing and performance,

A modular-packaging method of bare chips includes collecting bare chips to be square array and filling waster chip at blank position, placing said array on base plate of at least 3-layer printed circuit board, cutting out square hole at middle of clamp plate and sheathing said clamp plate at external of square array, covering top plate then setting square array upside down to take off base plate, coating conductive glue at chip back then covering base plate and baking them to form a flat plate, using photo-resist to fill seams, finalizing metal connections and sticking on top plate.

The invention relates to a standard cell test circuit layout and an optimization method thereof, and a standard cell test structure. The standard unit test circuit layout comprises a first to-be-tested unit circuit, wherein the first to-be-tested unit circuit comprises a plurality of stages of first standard units, and a plurality of stages of first standard units are arranged into a Y1-row*X1-column array. The connection relation of a plurality of stages of first standard units is realized in a fishbone-shaped manner, so the circuit layout area is saved; secondly, accuracy of the delay characteristic of the actually tested first standard unit is improved, so performance of the standard unit test circuit layout is improved.

A battery post connector and harness in accordance with the present invention includes a pair of generally rectilinear jaws with each jaw having a peripheral notch sized and shaped to fit against a battery post. The jaws are abuttable with the notches facing one another to encompass the battery post. A pair of spaced apart bolts are provided with each bolt passing through the jaw transverse to the battery post and each bolt includes a head on one end thereof and a nut on the other end thereof for tightening jaws against the battery post. This enables the bolt to attach the cables to the jaws in a parallel relationship with respect to one another.

The present invention discloses a sensor microsystem and a package method thereof. The method comprises the steps of: respectively manufacturing circuit layers covering a substrate at the front surface and the back surface of the substrate, and manufacturing metal through holes penetrating the substrate and electrically connected with the circuit layers at the back surface of the substrate; manufacturing a plurality of damming frames configured to fix a functional chip and a sensor chip on the circuit layer at the front surface of the substrate; assembling and electrically and mutually connecting the back surface of the functional chip and the top portions of the circuit layers between every two damming frames, wherein the functional chip comprises a processor chip or a controller chip; assembling and mutually connecting the back surface of the sensor chip and the front surface of the functional chip; filling the position between every two damming frames with flexible glue or silica gel covering the functional chip and the sensor chip to obtain a sensor microsystem wafer comprising the functional chip and the sensor chip. According to the invention, the sensor microsystem-level package is achieved, the working performance is high, the stress is low, and the universality is high.

The invention discloses a high-integration and high-reliability IGBT power module and a manufacturing method thereof. The high-integration and high-reliability IGBT power module comprises a metal bottom plate, metal bottom plate fixing holes, a multilayer wiring ceramic left half bridge substrate, a multilayer wiring ceramic switching substrate, a multilayer wiring ceramic right half bridge substrate, module pins, bonding wires, four IGBT chips and four diode chips which form an H bridge circuit structure. Process technologies such as mounting and bonding of a metal bottom plate, a multilayer ceramic substrate and a bare chip, metal fixed connection and the like are comprehensively adopted, a multilayer wiring ceramic left half bridge substrate, a multilayer wiring ceramic switching substrate and a multilayer wiring ceramic right half bridge substrate are mounted and welded on the metal bottom plate, and four IGBT chips and four diode chips are mounted and welded on corresponding substrates according to a design layout. The problems that an existing IGBT module is poor in high voltage resistance, low in assembly density, complex in heat dissipation measure and low in reliability are solved. The module is widely applied to the packaging process of semiconductor power devices.

The invention discloses a memory structure and a manufacturing method thereof. The memory structure comprises a plurality of storage units with the same structure; each storage unit comprises a storage module, a plastic package layer covers the storage module, a connecting piece is arranged at the bottom of the storage module, a metal column is arranged on the side edge of the storage module, andthe connecting piece extends to the side edge of the storage module and is electrically connected with the metal column; the plurality of storage units with the same structure are stacked, and the storage units positioned at the lower part are electrically connected with the connecting pieces of the storage units positioned at the upper part through the metal column. According to the invention, the capacity of the memory is expanded by stacking the memory modules, external leads are not needed, the interference among the leads is avoided, the manufacturing of the high-capacity memory is realized without a complex packaging process, complex chip assembly equipment is not needed, the packaging process is simple, and the cost is low.