Standard cell test circuit layout and optimization method thereof, and standard cell test structure

A standard unit and test circuit technology, applied in the direction of measuring electricity, measuring electrical variables, and electronic circuit testing, etc., can solve problems such as performance needs to be improved, and achieve the effect of saving area, improving performance, and improving accuracy

Active Publication Date: 2020-03-17
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, the performance of the existing standard unit test structure needs to be improved

Method used

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  • Standard cell test circuit layout and optimization method thereof, and standard cell test structure
  • Standard cell test circuit layout and optimization method thereof, and standard cell test structure
  • Standard cell test circuit layout and optimization method thereof, and standard cell test structure

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Experimental program
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Embodiment Construction

[0025] As mentioned in the background, the performance of the standard unit test structure in the prior art needs to be improved.

[0026] A standard unit test circuit layout, refer to figure 1 , including: a unit circuit to be tested; the unit circuit to be tested includes: an N-level standard unit 1001, the first-level standard unit 1001 to the N-th level standard unit 1001 are connected end to end; The first-level standard unit 1001 is connected to the Nth-level standard unit 1001, and the layout shape of the vibration-generating unit 1002 and the N-level standard unit 1001 forms a single ring.

[0027] figure 1 The placement of several standard units 1001 is simple and easy to control. But along with the quantity requirement of several standard units 1001 is more and more, promptly under the situation that the requirement to the test stage number of standard unit 1001 increases, make the length of described single-row ring too long, and the inside of described single-row...

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PUM

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Abstract

The invention relates to a standard cell test circuit layout and an optimization method thereof, and a standard cell test structure. The standard unit test circuit layout comprises a first to-be-tested unit circuit, wherein the first to-be-tested unit circuit comprises a plurality of stages of first standard units, and a plurality of stages of first standard units are arranged into a Y1-row*X1-column array. The connection relation of a plurality of stages of first standard units is realized in a fishbone-shaped manner, so the circuit layout area is saved; secondly, accuracy of the delay characteristic of the actually tested first standard unit is improved, so performance of the standard unit test circuit layout is improved.

Description

technical field [0001] The invention relates to the field of integrated circuit performance testing, in particular to a standard unit test circuit layout, an optimization method thereof, and a standard unit test structure. Background technique [0002] With the continuous development of integrated circuit design and manufacturing, the need for standard cell library design is increasing, and the subsequent delay and power consumption tests for the standard cell library are essential. However, due to the small delay of the standard cell, especially in the deep submicron process below 65 nanometers, the requirements for the test accuracy of the standard cell are becoming more and more stringent. So how to build a standard unit test structure to effectively and accurately evaluate the delay of the standard unit, so as to provide more accurate standard unit library design parameters to customers for reference, is an increasingly important research topic. [0003] However, the pe...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28
CPCG01R31/2882
Inventor 王夺陈志强唐伟峰张凤娟陈乃霞
Owner SEMICON MFG INT (SHANGHAI) CORP
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