53results about How to "Reduce logic" patented technology

Present invention discloses a high-speed memory requirement reduced low density check code decoder. It contains parameter calculating unit VPU module, verification node computing element CPU module and control logic module, wherein VPU module receiving decode sequence, memory said original information and starting iteration decode, in iterate decode process, CPU module and VPU module mutually transferring information each to proceed line and row operation, CPU storing verification operation result, controlling logical module to VPU module and CPU module cycle operation control, and outputting decode to obtain legal code word. Said invention fully utilizes minimal and decode algorithm to reduce memory requirement and height parallel to raise decode rate to shift LDPC code, saving message storage requirement and reaching faster decode speed and higher throughput rate.

The invention relates to an FPGA static timing analysis algorithm which specifically comprises the steps of extracting all timing paths existing in an entire circuit, checking whether signals meet therequirements of timing constraints when passing through the paths, and finding errors violating the timing constraints by analyzing a maximum path delay and a minimum path delay. According to the method, a critical path that makes the chip timing fail and has a decisive effect on the chip performance can be found more quickly.

The invention discloses a multistage serial-parallel conversion circuit, which is characterized by comprising at least three stages of D trigger groups. The first stage of D trigger groups comprises n cascaded D triggers with the same first clock signals; the second stage of D trigger groups comprises n*m cascaded D triggers with the same second clock signals; the third stage of D trigger groups comprises n*m cascaded D triggers with the same third clock signals; in the first stage of D trigger groups, the output end of the ath D trigger is connected with the input end of the ath D trigger in the second stage of D trigger groups; the output end of the ((m-1)*n+a)th D trigger in the second stage of D trigger groups is connected with the input end of the (m*n+a)th D trigger in the second stage of D trigger groups and is also connected with the input end of the ((m-1)*n+a)th D trigger in the third stage of D trigger groups; and n, m and a are all natural numbers, and a</=n.

The invention discloses a password encryption method for a social website. A password character string is subjected to strong disturbance before the conventional message-digest algorithm 5 (MD5) encryption is performed, so that the logicality of the encrypted character string is greatly reduced. Crypt encryption processing is performed before MD5 encryption is performed, so that the original text subjected to MD5 encryption is a character string without logical relationship. Hacker needs brand new original text/ciphertext control database which does not exist at present and has huge data to decipher the ciphertext, so the difficulty of ciphertext decipher by the hacker is greatly increased and the safety of the password is improved. The encryption flow is completely performed on the client side and the password character string input by a user does not pass through a server completely, therefore, even if the hacker breaks the firewall of the server, the hacker can only find the secret key and the ciphertext and cannot find the trace of the password character string, and the safety of the password is improved.

A clock distribution mechanism for circuit emulation applications, and related method, including one or more of the following: a plurality of digitally controlled oscillators, each of the plurality of digitally controlled oscillators receiving one or more Ethernet packets and generating a recovered clock from the one or more Ethernet packets; a multiplexer for receiving the recovered clocks generated by the plurality of digitally controlled oscillators, selecting a one of the recovered clocks generated by the plurality of digitally controlled oscillators, and outputting the selected one of the recovered clocks; a normalizer that receives a frequency of the selected one of the recovered clocks and generates a normalized frequency output based on the received frequency of the selected one of the recovered clocks and outputs the normalized frequency output; a clock source selector for receiving a plurality of input clock sources, one of the input clock sources being the normalized frequency output of the normalizer, the clock source selector selecting the normalized frequency output from among the plurality of input clock sources and transmitting the selected normalized frequency to a node; and one or more nodes for receiving the selected normalized frequency.

The invention discloses a configurable multiplication device of which hardware implementation can be applied to an AES and RSA mixed algorithm hardware circuit, and belongs to the field of cryptographic algorithm hardware implementation. Compared with an implementation scheme based on an ordinary multiplier in the past, the device has the advantages that a large number of configurable circuits are adopted by designing a special circuit structure, large-area multipliers and adders are reused, an AES MixColumn function and an RSA multiplication function are achieved in one operational circuit on the basis of additionally consuming a small number of selectors, and compared with the method of implementing the two kinds of operation singly, less circuit area is consumed, and less logic is used.

The invention provides a data processing method and device for an SSD and relates to the technical field of information processing. The method includes the steps that data is sent through a host and cached through a host cache; when nand needs to be written in, a mapping relationship is constructed through an FTL and then packed and sent to Media; Media disassembles the mapping relationship into acorresponding physical location to complete a write operation of the data; when the write operation goes wrong, the FTL re-constructs the mapping relationship and then packs and sends the mapping relationship to Media again till nand is successfully written in. The technical effects of simplifying logic and reducing flash memory operations are achieved.

The invention discloses a system message processing method and device for a live broadcast application. The method comprises the following steps: receiving a broadcast request of a system message; acquiring configuration information corresponding to the system message, the configuration information being used for configuring a format and a broadcast range of the system message; determining a broadcast range of the system message based on the configuration information, and formatting the system message to obtain a processed system message, the formatting being used for determining a content display style of the system message and/or a message template; and broadcasting the processed system message based on the broadcast range. According to the invention, the technical problems of poor flexibility and low efficiency of the implementation mode of the system message in related technologies are solved.

The invention provides a method for accessing a shared volume by a centralized gateway, which comprises the following steps of: S1, configuring a gateway on a gateway switch, and uploading messages of all storage switches to the gateway switch; S2, managing the sent messages by the gateway switch in a bucket classification mode; and S3, querying a required message, and performing matching to complete access. According to the shared volume access method provided by the invention, the centralized gateway is adopted to store the routing information, the logic on the service is reduced, the storage switch is dynamically added and deleted without modifying the service logic, the quick delivery of the service is realized, the routing of each sub-switch is kept independent, the error caused by the service logic is reduced, and the robustness of the service is improved.

The invention discloses a dual-power isolation circuit, system and method for intelligent driving, a normally-closed relay is connected in series in a dual-power system circuit, and the opening and closing of the normally-closed relay are controlled under the opening and closing of an engine starting control signal so as to control the isolation of a main power supply and an auxiliary power supply. The circuit is simple in structure, clear in logic, few in related components, free of interference and influence of other components, convenient to maintain and capable of being modified in a short time. The relay is low in cost, can be widely applied to circuits with dual-power systems, such as the field of intelligent automobiles, large-scale equipment mounting and refitting markets, motor homes and the like, and can effectively reduce the cost. And the cost can be effectively controlled in the modification of the intelligent automobile. The circuit design has no space limitation, can be arranged together with an automobile circuit, can effectively isolate intelligent equipment, a main power supply and an automobile auxiliary power supply when the starter works, does not consume electric energy, improves the utilization rate of the electric energy, and has a stable safety characteristic.

The invention provides a method for selecting an error correction circuit in a memory. ECC circuits with different performances are used for correcting data contents with different importance in the memory, so that the ECC circuits with the relatively high performances are used for correcting the data contents with the relatively high importance, and the ECC circuits with the relatively low performances are used for correcting the data contents with the relatively low importance, so as to avoid the power consumption waste caused by application of the same ECC circuits with the strong performances, and meanwhile, the logics of the ECC circuits, truly used at the any moment, are effectively reduced to reduce the soft error probability of the ECC circuit.