53results about How to "Reduce logic" patented technology

An optical modulator is formed to include a plurality of separate electrodes disposed along one arm, the electrodes having different lengths and driven with different signals to provide for multi-level signaling (e.g., PAM-4 signaling). By using separate drivers to energize the different sections, the number of sections energized at a given point in time will define the net phase shift introduced to the optical signal. The total length of the combined modulator sections is associated with a π phase shift (180°). Each section is driven by either a digital “one” or “zero”, so as to create the multi-level modulation. An essentially equal change in power between adjacent transmitted symbols is accomplished by properly adjusting the lengths of each individual section.

A method of incrementally reducing a design is disclosed. A logic verification tool receives a design and a property for verification with respect to the design, and then selects one or more of a plurality of diverse techniques for reducing the design. The logic verification tool then reduces the design to create a reduced design using the one or more techniques and attempts to generate a valid solution for the property on the reduced design. The logic verification tool determines whether a valid solution is generated, and, if not, replaces the design with the reduced design. Until a valid solution is generated, the logic verification tool iteratively performs the selecting, reducing, determining and replacing steps.

A method of incrementally reducing a design is disclosed. A logic verification tool receives a design and a property for verification with respect to the design, and then selects one or more of a plurality of diverse techniques for reducing the design. The logic verification tool then reduces the design to create a reduced design using the one or more techniques and attempts to generate a valid solution for the property on the reduced design. The logic verification tool determines whether a valid solution is generated, and, if not, replaces the design with the reduced design. Until a valid solution is generated, the logic verification tool iteratively performs the selecting, reducing, determining and replacing steps.

Accessing files in a physical data storage. The system may include an application programming interface (API) layer, the API layer including an API which extends the class Java.io.file to include methods for file access requests. The system may further comprise at least one internal layer, the internal layer configured to transform a file access request into a database call. Finally, the system may include a storage layer with a database, the database being configured to access the physical storage in response to the database call.

A data processing apparatus and method are provided for adding n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises determination logic operable to determine the larger operand of the first and second operands, and alignment logic operable to align the n-bit significand of the smaller operand with the n-bit significand of the larger operand. First adder logic is then operable to perform a first sum operation in order to generate a first rounded result in non-redundant form equivalent to the addition of the aligned significands with a rounding increment injected at a first predetermined rounding position appropriate for a non-overflow condition, the first adder logic comprising a single level of adder logic. Further, second adder logic is provided to perform a second sum operation in order to generate a second rounded result in non-redundant form equivalent to the addition of the aligned significands with a rounding increment injected at a second predetermined rounding position appropriate for an overflow condition, the second adder logic also comprising a single level of adder logic. Selector logic is then used to derive the n-bit result from either the first rounded result or the second rounded result.

A system and method for accurately modeling an asynchronous interface using expanded logic elements are provided. With the apparatus and method, the logic of an asynchronous interface is reduced to primitive logic elements. These primitive logic elements are expanded by the mechanisms of the present invention to take into consideration whether or not the primitive logic elements themselves may be experiencing a switching or glitch hazard and whether or not the inputs to the primitive logic elements may be based on a switching or glitch hazard from another primitive logic element in the asynchronous interface logic. These expanded logic elements are used in an integrated circuit design to replace the original primitive logic elements in the design. The asynchronous interface may then be simulated with the expanded logic elements providing outputs indicative of whether the actual data output of the expanded logic elements is deterministic or not.

A clock distribution mechanism for circuit emulation applications, and related method, including one or more of the following: a plurality of digitally controlled oscillators, each of the plurality of digitally controlled oscillators receiving one or more Ethernet packets and generating a recovered clock from the one or more Ethernet packets; a multiplexer for receiving the recovered clocks generated by the plurality of digitally controlled oscillators, selecting a one of the recovered clocks generated by the plurality of digitally controlled oscillators, and outputting the selected one of the recovered clocks; a normalizer that receives a frequency of the selected one of the recovered clocks and generates a normalized frequency output based on the received frequency of the selected one of the recovered clocks and outputs the normalized frequency output; a clock source selector for receiving a plurality of input clock sources, one of the input clock sources being the normalized frequency output of the normalizer, the clock source selector selecting the normalized frequency output from among the plurality of input clock sources and transmitting the selected normalized frequency to a node; and one or more nodes for receiving the selected normalized frequency.

The invention discloses a multistage serial-parallel conversion circuit, which is characterized by comprising at least three stages of D trigger groups. The first stage of D trigger groups comprises n cascaded D triggers with the same first clock signals; the second stage of D trigger groups comprises n*m cascaded D triggers with the same second clock signals; the third stage of D trigger groups comprises n*m cascaded D triggers with the same third clock signals; in the first stage of D trigger groups, the output end of the ath D trigger is connected with the input end of the ath D trigger in the second stage of D trigger groups; the output end of the ((m-1)*n+a)th D trigger in the second stage of D trigger groups is connected with the input end of the (m*n+a)th D trigger in the second stage of D trigger groups and is also connected with the input end of the ((m-1)*n+a)th D trigger in the third stage of D trigger groups; and n, m and a are all natural numbers, and a< / =n.