FPGA static timing analysis algorithm

Abstract

The invention relates to an FPGA static timing analysis algorithm which specifically comprises the steps of extracting all timing paths existing in an entire circuit, checking whether signals meet therequirements of timing constraints when passing through the paths, and finding errors violating the timing constraints by analyzing a maximum path delay and a minimum path delay. According to the method, a critical path that makes the chip timing fail and has a decisive effect on the chip performance can be found more quickly.

Description

technical field [0001] The invention is mainly used in the static timing analysis field of FPGA. Under the premise of providing logic units, corresponding connection relationships and known chip structures, timing analysis can be performed on specified netlist circuits. Background technique [0002] The premise of static timing analysis is that the designer first puts forward the requirements, and then the timing analysis tool will analyze according to the specific timing model and give the correct timing report. [0003] The main purpose of static timing analysis is to improve the main frequency of the system and increase the stability of the system. For many digital circuit designs, it is very important to increase the operating frequency, because high operating frequency means high processing power. Synthesis, mapping, placement, and routing of logic can be controlled through additional constraints to reduce logic and routing delays and thus increase operating frequency...

AI Technical Summary

Problems solved by technology

[0004] At present, the domestic timing analysis field lacks an accurate timing analysis method for analyzing various delay paths

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