A kind of multi-stage serial-to-parallel conversion circuit

Abstract

The invention discloses a multistage serial-parallel conversion circuit, which is characterized by comprising at least three stages of D trigger groups. The first stage of D trigger groups comprises n cascaded D triggers with the same first clock signals; the second stage of D trigger groups comprises n*m cascaded D triggers with the same second clock signals; the third stage of D trigger groups comprises n*m cascaded D triggers with the same third clock signals; in the first stage of D trigger groups, the output end of the ath D trigger is connected with the input end of the ath D trigger in the second stage of D trigger groups; the output end of the ((m-1)*n+a)th D trigger in the second stage of D trigger groups is connected with the input end of the (m*n+a)th D trigger in the second stage of D trigger groups and is also connected with the input end of the ((m-1)*n+a)th D trigger in the third stage of D trigger groups; and n, m and a are all natural numbers, and a< / =n.

Description

Technical field [0001] The present invention relates to the field of digital communication, and in particular to a multi-stage serial-to-parallel conversion circuit applied in a serializer / paralleler interface. Background technique [0002] The present invention relates to the field of electronic communication, serializer / deserializer (Serializer / DESerializer, SerDes). SerDes is an asynchronous data signal clock capture technology designed by a fully digital circuit, which is designed and implemented based on FPGA. A standard SerDes interface mainly includes the following modules: 8b / 10b encoder, 8b / 10b decoder, comma detector, parallel-to-serial converter, serial-to-parallel converter, clock and data recovery (CDR) , Digital Phase Locked Loop (Phase Locked Loop, PLL), etc. Among them, the parallel-serial converter and the serial-parallel converter are important modules designed by Serdes. They work the fastest in the entire circuit, which directly affects the jitter of the out...

AI Technical Summary

Problems solved by technology

Although the direct shift type serial-to-parallel converter can convert the 1-bit data signal input in series into the 10-bit data signal output in parallel, however, the number of bits of the flip-flop operating at a high-speed frequency is 10 bits, and the logic quantity during operation is large. , and because more devices work at the highest speed, the power consumption of the shift register structure is relatively large, which limits the maximum operating speed

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