5 results about "Significand" patented technology

An arithmetic unit implemented as an integrated circuit includes control logic configured to receive a control input representing a multiplication operation or a division operation and configure significand logic to perform a selected one of the multiplication operation and the division operation. The significand logic is configured to receive a first operand and a second operand and perform the selected operation on at least a portion of the first operand and at least a portion of the second operand.

A method of computing logarithms, comprising receiving a number, computing an exponent and significand of the received number, selecting a breakpoint value from a plurality of breakpoint values segmenting a range of the significand wherein the selected breakpoint value is the significand's greatest lower bound or lowest upper bound, computing a multiplication of the exponent and a logarithm value of two, computing a first intermediate value based on a least significant portion of the significand and an inverse value of the selected breakpoint value, computing an approximated logarithm value of a second intermediate value derived from the first intermediate value, computing a logarithm value of the significand by summing the approximated logarithm value and a logarithm value of the selected breakpoint value, computing a logarithm value of the received number by summing the logarithm value of the significand and the multiplication of the exponent and the logarithm value of two.

A decomposition circuit of an incoming binary number for a binary arithmetic operator, the incoming number having an FP32 floating-point format, the decomposition circuit being hardwired to decompose the incoming number into a pair of high and low components in an internal format with a 9-bit exponent and a 12-bit significand; directly connect the bits of the significand of the high component respectively to a circuit providing the value of the implicit bit and to the most significant bits of the fractional mantissa of the incoming number; directly connect the bits of the significand of the low component respectively to the remaining bits of the fractional mantissa; assign to the exponent of the high component the exponent of the incoming number plus 12; and assign to the exponent of the low component the unchanged exponent of the incoming number.

The invention relates to a binary input decomposition circuit (UPCK) for a binary arithmetic operator, the input number having an FP32 floating-point format. The decomposition circuit is wired to decompose the input number (X) into a pair of high and low components (Xh, Xl) in an internal format with a 9-bit exponent and a 12-bit significand. The circuit directly connects the bits of the significand (Xhm) of the high component to a circuit providing the value of the implicit bit and the most significant bits of the fractional mantissa of the input number. The circuit directly connects the bits of the significand (Xlm) of the low component to the remaining bits of the fractional mantissa. The exponent (Xhe) of the high component is set to the exponent of the input number (X) plus 12. The exponent (Xle) of the low component remains unchanged from the input number (X). Figure for the abstract: Fig. 1

A binary logic circuit for converting a number in floating point format into a fixed point format. An inverting hardware circuit inverts bit values of an exponent. A shifter coupled to the inverting hardware circuit receives a significand input comprising a contiguous set of the most significant bits of the significand and right-shifts the significand input by a number of bits equal to the value represented by p least significant bits of the inverted exponent to generate a shifter output, wherein p is dependent on an integer width iw or a fractional width fw. A multiplexer coupled to the shifter receives an input comprising a contiguous set of bits of the shifter output, and outputs the input if the most significant bit of the exponent is equal to zero.