11 results about "Significand" patented technology

An arithmetic unit implemented as an integrated circuit includes control logic configured to receive a control input representing a multiplication operation or a division operation and configure significand logic to perform a selected one of the multiplication operation and the division operation. The significand logic is configured to receive a first operand and a second operand and perform the selected operation on at least a portion of the first operand and at least a portion of the second operand.

The present application discloses floating-point addition. A floating-point addition circuit is provided for adding a first floating-point operand and a second floating-point operand, each of the first floating-point operand and the second floating-point operand including a significand and an exponent. An alignment shift circuit shifts the smaller operand significand based on the exponent difference to align with the larger operand significand. An increment circuit generates alternative versions of the larger operand significand, each version based on a different rounding increment applied to the larger operand significand. The addition circuit generates multiple candidate sum values, each candidate sum value representing the sum of the shifted smaller operand significand and one of the corresponding alternative versions of the larger operand significand. One of the candidate sum values ​​is selected as the rounded result of the addition of the first floating-point operand and the second floating-point operand. This allows for faster execution of the floating-point addition because the delay of the rounding increment can be hidden in the shadow of the alignment shift delay.

A method of computing logarithms, comprising receiving a number, computing an exponent and significand of the received number, selecting a breakpoint value from a plurality of breakpoint values segmenting a range of the significand wherein the selected breakpoint value is the significand's greatest lower bound or lowest upper bound, computing a multiplication of the exponent and a logarithm value of two, computing a first intermediate value based on a least significant portion of the significand and an inverse value of the selected breakpoint value, computing an approximated logarithm value of a second intermediate value derived from the first intermediate value, computing a logarithm value of the significand by summing the approximated logarithm value and a logarithm value of the selected breakpoint value, computing a logarithm value of the received number by summing the logarithm value of the significand and the multiplication of the exponent and the logarithm value of two.

A method and an apparatus for floating point processing are provided. The method includes receiving a first floating point operand and a second floating point operand, each having an n-bit format including a sign field, an exponent field, and a significand field; normalizing a binary value obtained by performing an arithmetic operation on fields corresponding to each other in the first floating point operand and the second floating point operand for an n-bit multiplication operation; determining whether the normalized binary value is a number representable in the n-bit format or an extended normal number not representable in the n-bit format; encoding the normalized binary value using an extended bit format in which an extension code identifying whether the normalized binary value is the extended normal number is added to the n-bit format according to a result of the determination; and outputting the encoded binary value using the extended bit format as a result of the n-bit multiplication operation.

Apparatuses, methods, computer readable media, and systems are disclosed in which a floating point processing instruction is decoded to generate control signals to trigger a floating point processing operation. In response to the control signals, the floating point processing operation is performed, comprising: performing processing that yields more than two floating point values; and performing, for each of the more than two floating point values: a determination of a shift value for a significand of that floating point value by subtracting an exponent value for that floating point value from a predetermined constant anchor value determined based on a maximum calculable product exponent for a product of the more than two floating point operands, and a shift of the significand by the shift value determined for that floating point value.

A decomposition circuit of an incoming binary number for a binary arithmetic operator, the incoming number having an FP32 floating-point format, the decomposition circuit being hardwired to decompose the incoming number into a pair of high and low components in an internal format with a 9-bit exponent and a 12-bit significand; directly connect the bits of the significand of the high component respectively to a circuit providing the value of the implicit bit and to the most significant bits of the fractional mantissa of the incoming number; directly connect the bits of the significand of the low component respectively to the remaining bits of the fractional mantissa; assign to the exponent of the high component the exponent of the incoming number plus 12; and assign to the exponent of the low component the unchanged exponent of the incoming number.

A floating-point accumulator circuit includes a floating-point input having an input significand field and a first shifter coupled to the input significand field and providing an output of the input significand field shifted by a first amount. A carry-save adder has a first, second, and third input and an output. The first input is coupled to the output of the first shifter and the output provides carry bits and sum bits representing a summation of the first input, the second input, and the third input as a significand of the accumulated value. Shifters are also coupled to the carry bits and the sum bits of the output of the carry-save adder to respectively provide the carry bits and the sum bits, both shifted by a second amount, to the second input and the third input of the carry-save adder.

Performing floating-point operations using an expanded-range floating-point format in processor devices is disclosed herein. In some aspects, a processor device comprises a floating-point unit (FPU) that is configured to perform a floating-point operation using one or more floating-point values interpreted by the FPU according to an expanded-range floating-point format that comprises no sign bit, a plurality of exponent bits including an additional exponent bit relative to a corresponding standard floating-point format, and a plurality of significand bits. The expanded-range floating-point format comprises a same number of bits as the corresponding standard floating-point format. A count of the plurality of significand bits of the expanded-range floating-point format is identical to a count of a plurality of significand bits of the corresponding standard floating-point format, and the significand bits of the expanded-range floating-point format are interpreted in a manner identical to the significand bits of the corresponding standard floating-point format.

A floating point processing instruction is decoded to generate control signals to trigger a floating point processing operation. In response to the control signals, the floating point processing opera

The invention relates to a binary input decomposition circuit (UPCK) for a binary arithmetic operator, the input number having an FP32 floating-point format. The decomposition circuit is wired to decompose the input number (X) into a pair of high and low components (Xh, Xl) in an internal format with a 9-bit exponent and a 12-bit significand. The circuit directly connects the bits of the significand (Xhm) of the high component to a circuit providing the value of the implicit bit and the most significant bits of the fractional mantissa of the input number. The circuit directly connects the bits of the significand (Xlm) of the low component to the remaining bits of the fractional mantissa. The exponent (Xhe) of the high component is set to the exponent of the input number (X) plus 12. The exponent (Xle) of the low component remains unchanged from the input number (X). Figure for the abstract: Fig. 1

A binary logic circuit for converting a number in floating point format into a fixed point format. An inverting hardware circuit inverts bit values of an exponent. A shifter coupled to the inverting hardware circuit receives a significand input comprising a contiguous set of the most significant bits of the significand and right-shifts the significand input by a number of bits equal to the value represented by p least significant bits of the inverted exponent to generate a shifter output, wherein p is dependent on an integer width iw or a fractional width fw. A multiplexer coupled to the shifter receives an input comprising a contiguous set of bits of the shifter output, and outputs the input if the most significant bit of the exponent is equal to zero.