20 results about "Leading zero" patented technology

The invention provides a floating-point number calculation circuit, a floating-point number calculation method, a storage medium and electronic equipment, and relates to the technical field of computers. In the circuit, a mantissa calculation module is used for executing multiplication of two floating-point number mantissas to obtain a product mantissa when a floating-point number operation starting signal is received; the leading zero detection module is used for responding to the floating-point number operation starting signal and performing leading zero detection on the mantissa of each floating-point number to obtain a leading zero estimation result of the product mantissa; the normalization processing module is used for executing product mantissa displacement control and index adjustment based on the leading zero estimation result to obtain a mantissa operation result and an index operation result; and the result output module is used for outputting a floating-point number product result based on the mantissa operation result and the index operation result. The length of the floating-point number multiplication calculation path can be effectively shortened, and the floating-point number calculation efficiency is improved.

The invention relates to the field of integrated circuit design, and discloses a processor preamble and mantissa continuous bit parallel counting device and method. The device comprises a 32-bit bit sequence flipping module, a 32-bit bit negation module, eight 4-bit leading zero detection modules, four 8-bit leading zero processing modules, two 16-bit leading zero processing modules, a 32-bit leading zero processing module and a 32-bit result output module. According to the invention, parallel counting can be carried out on leading zeros, leading 1, mantissa zeros or mantissa 1 of various data with different precisions in a single processor clock period, so that the required time sequence path length is greatly shortened, the higher processor clock frequency is realized, the multiplexing of a hardware circuit is realized, and the cost is reduced. The circuit greatly reduces the use of transistor resources, reduces the area of a chip, reduces the cost and power consumption of the chip, improves the operation efficiency, universality and adaptability of the processor, and is suitable for being applied to application scenes such as a high-performance digital signal processor and a CPU (Central Processing Unit).

The present application relates to trailing or leading digit predictors. A method and a leading zero predictor for estimating the number of leading zeros in the result of a fixed-point arithmetic operation, accurate to within one bit of any signed fixed-point number. The leading zero predictor comprises an input encoding circuit that generates an encoded input string from the fixed-point number; a window-based proxy string generation circuit that generates a proxy string by examining successive windows of the encoded input string and setting corresponding bits of the proxy string based on the examination, the leading ones of the proxy string being an estimate of the leading ones in the result of the arithmetic operation; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading ones in the proxy string.

The application provides a maximum value searching device for searching a maximum index in a plurality of integer source operands, the device comprising a first maximum value searching unit, wherein the first maximum value searching unit comprises: a first one-hot encoder for obtaining a plurality of source operands and generating a one-hot code corresponding to each source operand; a first bit-by-bit OR module for performing a bit-by-bit OR operation on the one-hot codes of the plurality of source operands and obtaining an intermediate result, wherein the bit-by-bit OR module is consistent with the code bit width of the one-hot encoder; a first leading zero searching module for searching the intermediate result to obtain a leading zero searching result, wherein the format of the leading zero searching result is a binary data format and the data bit width is consistent with the bit width corresponding to the plurality of source operands; and a first bit-by-bit NOT module for performing a bit-by-bit NOT operation on the leading zero searching result to obtain a maximum value in the plurality of source operands. The application can better meet the timing and area requirements.

This invention provides an optimized method for integrating floating-point multiply-accumulate algorithms in a single-precision floating-point multiply-accumulate unit. During the single-precision floating-point multiply-accumulate calculation, the pipeline is implemented as follows: P0 stage: The first pipeline stage receives three operands a, b, and c as input; it performs special value judgment, product mantissa calculation, product leading zero pre-statistics, and exponent difference and comparison logic; P1 stage: The second pipeline stage receives the multiplication result, compares the product exponent with the exponent of operand c, compares the exponent difference with the product leading zero, and performs exponent difference and product leading zero comparison; after exponent alignment, the mantissa of the aligned result is summed; P2 stage: The third pipeline stage receives the mantissa summed result, adjusts the exponent data, the sign bit to be operated on, and compares the results; after completion of normalization and rounding operations, the final result is adjusted accordingly, and abnormal states are judged. A single data path is used to ensure reuse of the same logic module within the pipeline, reducing area overhead.

The application provides a double-precision floating-point division calculation device, method and chip, relates to the technical field of computer chip design, and a pre-processing unit receives a dividend and a divisor in a double-precision floating-point format, detects the number of leading zeros of the mantissas of the two, and determines the exponent attribution of a quotient result in combination with the exponent values; if the quotient result is a non-normalized number, the corresponding right shift amount is determined according to the exponent attribution. A dynamic iteration unit generates an iteration total number control signal according to the right shift amount, accesses a look-up table to output a quotient value candidate based on the specific high bit combination of the remainder and the divisor in each clock cycle, updates the remainder, synchronously generates and adjusts a quotient value selection function, and left shifts the effective quotient value of each round according to the remaining iteration number and the right shift amount. A post-processing unit outputs a double-precision floating-point division result according to the final quotient value selection function, the sign and value of the remainder of the last round and a preset rounding rule when the iteration is completed. The application reduces the operation delay and power consumption.

The invention discloses a time sequence floating-point number exclusive-or compression-oriented processing method and device and a readable storage medium, and relates to the technical field of computers. The problems that an existing XOR operation compression method highly depends on the number of leading zeros and trailing zeros in an original XOR result value, the compression efficiency of the XOR operation compression method is affected, and the size of a computer storage space is occupied are solved. According to the processing method provided by the invention, the number of leading zeros and trailing zeros in the accumulated exclusive-or value is increased, so that the floating-point number time sequence is more suitable for the exclusive-or compression method, the occupied storage space after compression is saved, and the compression efficiency is improved. The invention is mainly used for improving the occupied storage space of the computer.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for protecting HLL-derived results with differential privacy. In one aspect, a method includes receiving a set of sketches from a set of data owners. Each sketch represents a sampling of items in a dataset and comprising a set of registers that store values representing a number of leading zeros. A minimum register value for the sketches is determined based on differential privacy parameters. The sketches are merged to generate a merged sketch. The merging includes storing the minimum register value in each register of the merged sketch that has a value that is less than the minimum register value. A number of unique items represented by the merged sketch is estimated. The estimating includes adding noise to the estimated number of unique entities. Data indicating the estimated number of unique entities is provided to a recipient.

The invention provides a double-precision floating-point division calculation device and method and a chip, and relates to the technical field of computer chip design, a preprocessing unit receives a dividend and a divisor in a double-precision floating-point format, detects the number of leading zeros of mantissas of the dividend and the divisor, and determines the index attribution of a quotient result in combination with an index value; and if the quotient result is a non-normalized number, determining the corresponding right shift amount according to the index affiliation. A dynamic iteration unit generates a total iteration number control signal according to the right shift amount, and accesses a lookup table to output a quotient value candidate based on a specific high bit combination of a remainder and a divisor in each clock period; updating the remainder; synchronously generating and adjusting a quotient value selection function; and performing left shift on the effective quotient value of each round according to the number of residual iterations and the right shift amount. And the post-processing unit outputs a double-precision floating-point division result according to a final quotient value selection function, a last-round remainder symbol and value and a preset rounding rule when iteration is completed. According to the invention, operation delay and power consumption are reduced.

This invention provides a method for optimizing the area of ​​a double-precision multiply-accumulator based on pipelined pause technology. Considering the application scenarios of double-precision floating-point data, while meeting the performance requirements of most double-precision floating-point computation scenarios, the method improves the multiply-accumulator algorithm by changing the dual data path to a single data path during the double-precision floating-point multiply-accumulator computation process. By combining this with real-world application scenarios, it ensures that performance loss due to pipelined pauses is not incurred in common situations. For special low-probability events, performance is sacrificed by reducing the area of ​​the multiply-accumulator. The bit width is reduced based on the actual statistical situation of the operator, and pipelined pause multiplexing logic blocks are used to improve the area of ​​the adder, shifter, and leading zero statistics module, thereby improving the area of ​​the multiply-accumulator module.

The application provides a multi-precision floating point fused multiply-add structure and a microprocessor architecture, the floating point fused multiply-add structure comprising: in the first stage pipeline, an input preprocessing module decomposes input operands to obtain a sign bit, an exponent bit and a mantissa bit; a Booth encoder generates partial products through a base-4 Booth encoding algorithm, and a tree array multiplier compresses the partial products into three groups; in the second stage pipeline, a CSA4-2 compression adder compresses the three groups of partial products and the mantissa bit after shift alignment into two groups; an adder module sums the two groups of partial products to obtain a mantissa summation result; in the third stage pipeline, a leading zero detection module detects the leading zero of the mantissa summation result, and adjusts the exponent and the mantissa to obtain a normalized result; in the fourth stage pipeline, the floating point data is rounded. The application improves the operation performance, energy efficiency ratio and adaptability of the floating point fused multiply-add structure, thereby balancing the high performance and high energy efficiency of the microprocessor.

This invention relates to the field of integrated circuit design and discloses a parallel counting device and method for consecutive leading and mantissa bits in a processor. The device includes a 32-bit bit order reversal module, a 32-bit bit inversion module, eight 4-bit leading zero detection modules, four 8-bit leading zero processing modules, two 16-bit leading zero processing modules, a 32-bit leading zero processing module, and a 32-bit result output module. This invention enables parallel counting of leading zeros, leading ones, mantissa zeros, or mantissa ones for various data with different precisions within a single processor clock cycle. This significantly shortens the required timing path length, allowing for higher processor clock frequencies. It also enables hardware circuit reuse, greatly reducing transistor resource usage, chip area, chip cost, and power consumption. This improves the processor's operational efficiency, versatility, and adaptability, making it suitable for applications in high-performance digital signal processors and CPUs.

Devices and methods are provided for performing, by a processor in response to a floating point multiply instruction, multiplication of floating point numbers. An example processor includes first, second, third, and fourth computational paths. In operation, the first determines values of implied bits of mantissas of floating point numbers and generates first partial product terms, the second multiplies remainders of the mantissas to generate second partial product terms, the third detects a number of leading zeros in the mantissas and determines a shift amount for each of the mantissas, and the fourth calculates exponents for a flush-to-zero mode.

This application relates to an embedded coding method, apparatus, computer device, storage medium, and computer program product. The method comprises: obtaining data to be coded, generating a mantissa matrix based on the data to be coded; performing a trapezoidal structure test on the mantissa matrix to obtain the number of leading zeros corresponding to each row of data in the mantissa matrix; obtaining each bit group in the mantissa matrix based on the number of leading zeros corresponding to each row of data; and encoding the data to be coded based on each bit group in the mantissa matrix to obtain target coded data. This method can effectively improve the coding rate of embedded coding.

This invention discloses a blockchain system based on a parallel chain structure and its construction method, comprising: multiple parallel chains, each chain used to record transactions and constructing the ledger using the heaviest subtree principle. Each block, after creation, is assigned a random weight based on the number of leading zeros in its hash value; the block creation process is decoupled from the on-chain process, and after a node successfully mines, if there are k chains in the system, the chain to which the block is added is determined based on the last log2k bits of the block's hash value. This invention uses multiple parallel chains as the ledger structure, decoupling block creation from on-chain processing, thereby distributing the computing power of malicious nodes to enhance the security of the entire system. Utilizing the randomness and uniform distribution of hash values, a random weight assignment mechanism based on hash values ​​is designed to reduce the convergence time of each chain and the confirmation latency of blocks.

The application discloses a switchable precision floating-point multiplier-adder, which comprises a four-stage pipeline, a first-stage pipeline, a second-stage pipeline, a third-stage pipeline and a fourth-stage pipeline; the first-stage pipeline comprises a distribution processing module, a multiplier array module, an adder array adding module and an exponent comparison module; the second-stage pipeline comprises an exponent difference module, an alignment shift module, an addition tree module and a compression module; the third-stage pipeline comprises a leading zero prediction module, a leading zero coding module, a sign prediction module and an advance calculation module; and the fourth-stage pipeline comprises a sum and rejection module and an exponent normalization module. The floating-point multiplier-adder combines double-precision multiplication and addition to complete double-precision floating-point operation in the form of A+BxC, and the combination can greatly reuse the components in the multiplier-adder compared with a simple multiplier-adder combined with an adder. The application can be widely applied in the field of hardware operation devices.

The invention discloses a processing method and device for floating-point number mantissa leading zero detection and computer equipment, and relates to the technical field of floating-point exponential calculations, in response to a floating-point number multiply-add operation instruction, fusion multiply-add operation is performed on an input first operand, an input second operand and an input third operand; wherein the first operand, the second operand and the third operand are floating-point numbers generated in the artificial intelligence model training or reasoning process, and then responding to mantissa multiply-add fusion in the fusion multiply-add operation, according to mantissa digits in the second operand and mantissa digits in the third operand, calculating the mantissa of the second operand according to the mantissa digits in the third operand. Determining a target detection mantissa bit width, which is smaller than all mantissa bits of the mantissa multiply-add fusion result, of leading zero detection of the mantissa multiply-add fusion result, and performing leading zero detection on the mantissa multiply-add fusion result according to the target detection mantissa bit width in response to leading zero detection in the fusion multiply-add operation, and obtaining the number of leading zeros in the mantissa of the mantissa multiply-add fusion result.

This application provides a data accumulation method, accumulator, chip, and electronic device. The method includes: acquiring an instruction; the instruction includes an identifier for the data to be processed and the type of the data to be processed; the type is either a floating-point number or a fixed-point number; based on the identifier, sequentially reading a group of data; wherein each group includes a number of processed data, mC is the minimum processing amount per operation, nB is the number of bits in any processed data, and is a floor function; for each group, performing Wallace tree-based compression based on the type, performing leading zero detection on the compression result, and obtaining the accumulation result of the group of data. The method provided in this application reads a group of data sequentially based on the identifier in the instruction; wherein each group includes a preset number of processed data; for each group, performing Wallace tree-based compression based on the type, performing leading zero detection on the compression result, and obtaining the accumulation result of the group of data, thereby accelerating the data processing speed and improving processing efficiency.

This invention aims to solve the optimization problem of fused dot product addition in support of multiple low-bit-width floating-point numbers with correct rounding under the same input length, and proposes a fused dot product addition calculation device and method for multiple low-bit-width floating-point numbers. The calculation device includes the following modules: input segmentation and detection module, sign processing module, exponent processing module, mantissa processing and calculation module, anomaly detection module, mantissa data path module, leading zero detection module, mantissa normalization module, rounding module, exponent adjustment module, normal output module, anomaly output module, and output module. The method is based on the analysis of the mantissa data path, and proposes and uses a new mantissa shifting method for FP4 and FP6; for FP8, it proposes and uses a mantissa allocation scheme that can achieve correct rounding. In addition, a comparison and sorting scheme for the exponent of low-bit-width floating-point numbers is proposed, thereby enabling fused dot product addition calculation of multiple low-bit-width floating-point numbers with correct rounding.

This invention relates to the field of artificial intelligence technology, and in particular to a computation method and arithmetic unit based on the Posit data format. The method includes obtaining the sign bit, exponent extension bit, mantissa bit, and exponent bit of the Posit data format; preprocessing each position of the Posit data format; defining a bit width allocation priority rule; multiplying the two mantissa bits obtained from decoding to obtain a mantissa product and a mask sequence; determining the number of leading zeros in the mantissa product based on the mask sequence; performing a unified logical shift on the mantissa product; rounding the shifted mantissa part; converting the mantissa product into a fixed-point number format based on the sign bit, exponent extension bit, and exponent bit; performing addition based on the fixed-point number; and outputting the accumulated result. This invention uses one-complement encoding, and the input / output processing only requires logical inversion to complete the sign-related operation, reducing circuit area and power consumption, eliminating the need for complex timing control, and reducing logic resource consumption.