5 results about "Leading zero" patented technology

This invention provides an optimized method for integrating floating-point multiply-accumulate algorithms in a single-precision floating-point multiply-accumulate unit. During the single-precision floating-point multiply-accumulate calculation, the pipeline is implemented as follows: P0 stage: The first pipeline stage receives three operands a, b, and c as input; it performs special value judgment, product mantissa calculation, product leading zero pre-statistics, and exponent difference and comparison logic; P1 stage: The second pipeline stage receives the multiplication result, compares the product exponent with the exponent of operand c, compares the exponent difference with the product leading zero, and performs exponent difference and product leading zero comparison; after exponent alignment, the mantissa of the aligned result is summed; P2 stage: The third pipeline stage receives the mantissa summed result, adjusts the exponent data, the sign bit to be operated on, and compares the results; after completion of normalization and rounding operations, the final result is adjusted accordingly, and abnormal states are judged. A single data path is used to ensure reuse of the same logic module within the pipeline, reducing area overhead.

The application provides a double-precision floating-point division calculation device, method and chip, relates to the technical field of computer chip design, and a pre-processing unit receives a dividend and a divisor in a double-precision floating-point format, detects the number of leading zeros of the mantissas of the two, and determines the exponent attribution of a quotient result in combination with the exponent values; if the quotient result is a non-normalized number, the corresponding right shift amount is determined according to the exponent attribution. A dynamic iteration unit generates an iteration total number control signal according to the right shift amount, accesses a look-up table to output a quotient value candidate based on the specific high bit combination of the remainder and the divisor in each clock cycle, updates the remainder, synchronously generates and adjusts a quotient value selection function, and left shifts the effective quotient value of each round according to the remaining iteration number and the right shift amount. A post-processing unit outputs a double-precision floating-point division result according to the final quotient value selection function, the sign and value of the remainder of the last round and a preset rounding rule when the iteration is completed. The application reduces the operation delay and power consumption.

This invention provides a method for optimizing the area of ​​a double-precision multiply-accumulator based on pipelined pause technology. Considering the application scenarios of double-precision floating-point data, while meeting the performance requirements of most double-precision floating-point computation scenarios, the method improves the multiply-accumulator algorithm by changing the dual data path to a single data path during the double-precision floating-point multiply-accumulator computation process. By combining this with real-world application scenarios, it ensures that performance loss due to pipelined pauses is not incurred in common situations. For special low-probability events, performance is sacrificed by reducing the area of ​​the multiply-accumulator. The bit width is reduced based on the actual statistical situation of the operator, and pipelined pause multiplexing logic blocks are used to improve the area of ​​the adder, shifter, and leading zero statistics module, thereby improving the area of ​​the multiply-accumulator module.

The application discloses a switchable precision floating-point multiplier-adder, which comprises a four-stage pipeline, a first-stage pipeline, a second-stage pipeline, a third-stage pipeline and a fourth-stage pipeline; the first-stage pipeline comprises a distribution processing module, a multiplier array module, an adder array adding module and an exponent comparison module; the second-stage pipeline comprises an exponent difference module, an alignment shift module, an addition tree module and a compression module; the third-stage pipeline comprises a leading zero prediction module, a leading zero coding module, a sign prediction module and an advance calculation module; and the fourth-stage pipeline comprises a sum and rejection module and an exponent normalization module. The floating-point multiplier-adder combines double-precision multiplication and addition to complete double-precision floating-point operation in the form of A+BxC, and the combination can greatly reuse the components in the multiplier-adder compared with a simple multiplier-adder combined with an adder. The application can be widely applied in the field of hardware operation devices.