107 results about "Hardware random number generator" patented technology

The present invention provides a system and method for introducing white noises into a digital audio signal so that there is progressive and cumulative degradation in audio quality after each successive reproduction of the audio sound signal in a fashion analogous to analog audio reproduction. The invention provides a white noise generator, and a digital entroping unit. In a preferred embodiment, the white noise generator is implemented by a hardware random number generator. The digital entroping unit controls the magnitude of white noise desired based on a random number generated by the random number generator, and adds the white noise to the input audio sound signal to produce a degraded audio sound signal. The magnitude of white noise can be controlled by using various masking and formatting of random number data.

The invention provides a security system and methods for high level transactions between devices. The system includes a non-deterministic hardware random number generator to provide multi-level encryption between a remote and host device.

A random number generator has a simple configuration using know inexpensive electronic parts and can generate the true physical random numbers at a required generation speed. Such a random number generator can provide the true physical random numbers to any sectors of society at dramatically low cost A random pulse generator comprises a thermal noise generating element (2) having a resistor, a conductor or a semiconductor such as a diode adapted to generate thermal noises Hen no electric current is supplied to them, an analog-amplifier circuit for amplifying the irregular potential generated from the thermal noise generating element and a waveform shaping circuit (6) adapted to take out the output of the amplifier circuit as random rectangular pulse signals. A thermal noise random number generator comprises, in addition to the above components, an n-bit counter (n being an integer) for measuring the time interval between a random pulse signal output from the waveform shaping circuit (6) and the immediately succeeding random pulse signal and is adapted to output the count of the n-bit counter as natural random number.

The present invention is a method and apparatus for testing random numbers generated by a random number generator in real time. As random numbers are generated, overlapping blocks of k bits undergo an exponential count operation one at a time, in which the count operation is performed by dropping the leftmost bit from the previous k bit block and appending a new random bit to the right of it to form a new k bit block, thus maintaining the size of the block. The binary value of this k bit block is used for performing the accumulator selection during the overlapping count operation. All of the outputs of the exponential averaging are compared to a predetermined acceptance range to determine whether the bits generated by the random number generator is sufficiently random.

The invention discloses a photon-number distinguishable detection-based true random number generator and belongs to the class of quantum secure communication. Different photon-number incident events are combined into a 2-bit random number sequence according to the uncertainty principle of poisson distribution by using the characteristics of a photon-number distinguishable detector capable of distinguishing incident photon numbers. The true random number generator mainly comprises a photon-number distinguishable detection module, a photon-number identifying and processing module and a random number acquisition module and can generate high-speed random secret keys needed in the quantum secure communication. The true random number generator has stable and reliable random sources; the generated true random number cannot be repeated or deciphered by the random characteristics of light quanta; a complex post-processing procedure is not needed; and the true random number generator is convenient to use.

The invention discloses a true random number generator based on a digital circuit. The true random number generator comprises a random number source generating module used for generating digital signals with random character, and a postprocessing module used for conducting algorithm processing on the digital signals with random character, conducting detection and then generating true random number signals, wherein the postprocessing module comprises a first exclusive-OR gate circuit, a linear feedback shift register, a detection circuit and an FIFO memory which are sequentially connected, the input signals of the first exclusive-OR gate circuit are the digital signals with random character, the input signals of the linear feedback shift register are signals generated after the digital signals with random character and feedback signals of the linear feedback shift register are subjected to exclusive-OR by the first exclusive-OR gate circuit, and the detection circuit detects the digital signals with random character with a predetermined detection algorithm so as to generate true random number data and stores the true random number data in the FIFO memory. The true random number generator is simple in circuit structure, low in cost and high in adaptability.

The invention discloses an FPGA-based true random number generator. The FPGA-based true random number generator comprises an oscillating ring circuit, a multi-tap signal delay chain, a trigger array, a logic XOR circuit and a postprocessing circuit. A clock signal generated by the oscillating ring circuit is fed into the signal delay chain, the trigger array samples the level states of all taps of the delay chain under the control of a system clock, acquisition results of all triggers are subjected to logic XOR processing and sent into the postprocessing circuit, and output of the postprocessing circuit is a generated binary true random number sequence. The FPGA-based true random number generator not only can generate random numbers at a rate as high as possible, but also can guarantee the quality of the random numbers.

A filtering apparatus in a hardware random number generator that prevents the random number generator (RNG) from outputting a contiguous string of zeros or ones longer than a specified length. The maximum length is programmable in the apparatus. The apparatus includes a counter that keeps a current count of contiguous zero bits in a series of bytes generated by the RNG. An adder generates a sum of the current zero bit count and the number of leading zeros in the next byte generated. If the sum exceeds the maximum length, then the filter throws out the byte rather than accumulating it. Otherwise, if the byte contains all zeros, the counter is updated with the sum; or if the byte contains trailing zeros, the counter is updated with the number of trailing zeros; otherwise the counter is cleared. The apparatus does the same for contiguous one bits.

The invention discloses a high-speed generation method of true random numbers. The high-speed generation method comprises the following steps of forming metastable ring oscillators with a plurality of metastable sub ring oscillators, allowing the metastable sub ring oscillators to work in a stable oscillation state or a metastable state alternately via a control signal, connecting a multiplexer with the metastable ring oscillators as entropy sources, generating a first random sequence and a second random sequence with the two independent entropy sources respectively, inputting the random sequences in an encryption operation unit, performing encryption operation by taking the first random sequence as plaintext data and the second random sequence as a key, and outputting ciphertext data as random number output. Compared with the prior art, a true random number generator is achieved in an encryption mode; isostatic correction is performed on the generated random number via an exclusive-or chain and a DES (data encryption standard) algorithm to achieve a combination of the random numbers generated by the two ring oscillators; and finally, a random number generation rate reaches 400 Mbit/s.

The invention discloses a high-speed true random number generator. The true random number generator comprises a first feedback ring oscillation true random source, a second feedback ring oscillation true random source and an encryption operation unit, wherein the first feedback ring oscillation true random source is used for generating a first random sequence; the second feedback ring oscillation true random source is used for generating a second random sequence; and the encryption operation unit performs encryption operation by taking the first random sequence as plaintext data and taking the second random sequence as a key, and outputs ciphertext data as a random number. Compared with the prior art, the true random number generator consists of only general logic units, so that system integration is very easy; meanwhile, the true random number generator is realized in an encryption manner; the generated random number is subjected to isostatic correction through an XOR chain and a DES algorithm to realize that two ring oscillators generate a combination of random numbers; and finally the random number generation rate reaches 400Mbit/s.

The invention discloses a true random number generator with a digital post-processing circuit, which comprises a true random number source and a true random number output register. The true random number generator is characterized in that the digital post-processing circuit is connected between the true random number source and the true random number output register, wherein the digital post-processing circuit comprises a Manchester encoder, a linear feedback shift register and a DES (data encryption standard) encryption unit which are connected from the true random number source to the true random number output register; the true random number output register is used for latching the ciphertext output by the DES encryption unit; and finally, the true random number is output to a chip by the true random number output register. The true random number generator improves the quality of random number sequences generated by the true random number source; the finally output random number sequences have the characteristics of good uniformity and high independence; the security for information storage of the cryptographic chip is improved; and the true random number generator has higher actual application value in the aspects of cryptographic chip, information security and the like.

Apparatus for generating a truly random binary bit value in which the resistance of memristive devices serve as the analogue bit values. Resistance values and the randomness by which they are generated stems from the inherently non-uniform, irreproducible variations in the materials of which the system is composed.

The invention relates to a dynamic true random number generator, which is composed of a true random source Von Neumann checker, a packet hybrid network and a dynamic control component. The data generated by the true random source is input into the Von Neumann checker, and the output terminal of the Von Neumann checker is connected with the input terminal of the packet hybrid network; the packet hybrid network comprises a chaos transformation component, a discretization component and a block cipher component, the output terminal of the chaos transformation component is adjusted through the block cipher component after passing through the discretization component, the dynamic control component controls the structure of the chaos transformation component through signals and/or the parameter of the nonlinear component in the block cipher component to ensure the sequence outputting of the packet hybrid network to evolve in the direction according with the test standard along the working process, and the final output obtained from the packet hybrid network according with the test standard is a true random number sequence. The true random number generator can generate high-quality and high-stability true random number sequence, can resist various attacks by the dynamic structure, and has high security.

Two or more numerical samples are read from a storage location (or many storage locations) and the samples are compared to generate a single bit of entropy. This method is repeated to populate two arrays which are also compared to generate a single bit. Comparison of the arrays is also repeated to generate a sequence of bits which are formed into computer words. The words are combined with a shift register to generate a seed block array of any length. The seed block array is used to seed a pseudo random number generator. The storage location is a register, accumulator, buffer, clock, address, memory location, etc., that changes periodically. Comparison may be performed by counting the number of certain types of bits in the two values and returning a one or zero depending upon the count.

The invention provides a high-speed physical random number generator based on a chaos laser entropy source. The high-speed physical random number generator based on the chaos laser entropy source comprises an entropy source module and a post-processing module. The entropy source module is used for emitting two routes of broadband chaotic signals of which a time delay feature can be inhibited and abandwidth can be reinforced, and cross correlation between the two routes of the chaotic signals is lower. The post-processing module is used for, after converting the two routes of the chaotic signals into a digital signal, processing to obtain a high-speed random number finally. Compared with a pseudo random number generator, the generated random number has not periodicity, and the random number with a random length which cannot be regenerated can be generated. Compared with a traditional physical random number generator, an entropy source bandwidth is larger, and reaches up to tens of GHz.The high-speed physical random numbers with hundreds of Gbits/s of a code rate can be obtained.

An F-RAM authenticating memory device and method providing secure mutual authentication between a Host system and a memory in order to gain read/write access to the F-RAM user memory contents. The device and technique of the present invention uses an Advanced Encryption Standard AES128 encryption module in conjunction with a true hardware random number generator and basic exclusive OR (XOR) functions in order to achieve a secure algorithm with a relatively small amount of processing. Due to inherently faster write times than that of conventional floating gate non-volatile memory technologies, the use of F-RAM significantly reduces the time available to interfere with a critical security parameter (CSP) update. Moreover, unlike floating gate technologies, F-RAM's read vs. write current signature is balanced making it less prone to side channel attacks while also providing relatively faster erase times.

The invention discloses a true random number generator based on time delay feedback oscillators. The true random number generator mainly solves the problems that a true random number generator in the prior art is low in true random number generating speed and poor in randomness. The true random number generator comprises an oscillating circuit and a sampling circuit. The oscillating circuit is used for generating random oscillating signals and is composed of a plurality of time delay feedback exclusive-or oscillators and a plurality of time delay feedback exclusive-nor oscillators, each time delay feedback exclusive-or oscillator is composed of an exclusive-or gate and three upper inverter sets, each time delay feedback exclusive-nor oscillator is composed of an exclusive-nor gate and three lower inverter sets, and the inverter sets comprise different numbers of inverters. The sampling circuit is used for sampling the random oscillating signals generated by the oscillating circuit and is composed of a plurality of D triggers and an exclusive-or gate, and output of all the D triggers generates true random numbers with the speed of 100 Mbit/s or above through the exclusive-or gate. The true random number generator is simple in structure and good in entropy source randomness and can be used for secret communication.

A random number generator comprises random number generation circuitry to generate and output random bits. The random number generator comprises interface circuitry to receive and store random bits output by the random number generation circuitry and to output random bits. The interface circuitry prevents outputting the same random bits more than once.

The invention relates to a true random number generation method. The method comprises the following steps: S1, generating three groups of independent physical random signals by adopting a continuous light source; s2, generating a binary true random number stream based on the three groups of physical random signals; and S3, verifying the security and randomness of the true random number in the binary true random number stream by adopting a random statistical test packet. The invention further relates to a true random number generation system, which comprises: a light source random signal generation device for generating three groups of independent physical random signals; a binary true random number generation device which is used for generating a binary true random number stream based on the three groups of physical random signals; and a verification device which is used for verifying the safety and randomness of the true random numbers in the binary true random number flow by adoptinga random statistical test packet. By implementing the true random number generation method and system provided by the invention, the high-quality random number with unpredictability and irreversibility can be simply generated at a high speed by adopting a common physical random signal source.

The present invention is a method and apparatus for testing random numbers generated by a random number generator in real time. As a series of random numbers are generated, a number of bits that have the value of a predetermined logic value at a specific, predefined range of intervals is determined and then applied to an exponential averaging operation (A). Thereafter, it is determined whether the generated random numbers are predictable by comparing the output of all said exponential operations to their predetermined acceptance range.

The invention relates to an on-chip true random number generator, which comprises a random noise generator, an AD (Analog to Digital) sampler, a noise converter and a sequence generator. The on-chip true random number generator is characterized in that an on-chip temperature sensor is used as a noise source of the true random number generator; a temperature value is converted into a digital signal through AD sampling; the digital signal obtained through sampling is subjected to noise extraction conversion, and a group of true random sequences is obtained; and finally, a plurality of groups of random sequences are assembled through the sequence generator, and true random numbers in any bit are generated. An on-chip noise signal is used as a signal source of the true random number, so the characteristics of randomness, unpredictability and the like are realized, and the generated random numbers are in uniform distribution, comfort to the characteristics of irrelevance and the like and belongs to high-quality true random numbers. The on-chip true random number generator belongs to an on-chip true random number generator realized by using an integrated circuit; the technologies of chip design production line, synchronous processing, resource reuse and the like are utilized; and the on-chip true random number generator has the advantages that the cost is low, the stability is good, the velocity is high, the realization is easy, and the like.

The invention discloses a network cipher machine. A system central processing unit (CPU) in the cipher machine is in control connection with a packet encryption algorithm chip, a hardware random number generator, a memory, a casing protection monitoring circuit and a static random access memory (SRAM) device with a backup battery respectively, wherein the casing protection monitoring circuit protects the SRAM device with the backup battery; and simultaneously the system CPU is externally connected with two Ethernet ports by two physical layer transceivers, and is externally connected with a serial port by a serial port controller. The network cipher machine adopts a virtual private network (VPN) technology, constructs a virtual private network on the Internet or a private network, makes networking easier and makes security simpler to achieve.