FPGA-based true random number generator

Abstract

The invention discloses an FPGA-based true random number generator. The FPGA-based true random number generator comprises an oscillating ring circuit, a multi-tap signal delay chain, a trigger array, a logic XOR circuit and a postprocessing circuit. A clock signal generated by the oscillating ring circuit is fed into the signal delay chain, the trigger array samples the level states of all taps of the delay chain under the control of a system clock, acquisition results of all triggers are subjected to logic XOR processing and sent into the postprocessing circuit, and output of the postprocessing circuit is a generated binary true random number sequence. The FPGA-based true random number generator not only can generate random numbers at a rate as high as possible, but also can guarantee the quality of the random numbers.

Description

technical field [0001] The invention belongs to the field of digital circuit design, and in particular relates to an FPGA-based digital circuit design technology. Background technique [0002] True random number generators are important components in modern encrypted communication systems. In addition to the high quality of the generated true random numbers, the rapid development of encrypted communication technologies in recent years, such as quantum key distribution systems, requires true random number generators to be able to generate high-speed random number bit streams in real time. At present, the practical quantum key distribution system has reached 1 to 10Gbps for the generation rate of random number bit stream. The principle of true random number generation is to rely on some uncontrollable physical phenomena (entropy sources) to generate unpredictable random numbers. The upper limit of the random number generation rate is generally determined by the characteristic...

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Problems solved by technology

[0003] The technical problem to be solved by the present invention is that exis

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