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FPGA-based true random number generator

A true random number and generator technology, applied in the field of FPGA-based digital circuit design, can solve the problem that the random number generator cannot generate random numbers at the highest rate, and achieve the effect of ensuring quality

Active Publication Date: 2016-08-17
UNIV OF SCI & TECH OF CHINA
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  • Abstract
  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

[0003] The technical problem to be solved by the present invention is that existing random number generators cannot generate random numbers at the highest rate

Method used

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  • FPGA-based true random number generator

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Embodiment Construction

[0019] As we all know, the oscillation ring circuit will oscillate spontaneously, and the signal output by any node on the oscillation ring circuit is a clock signal. The oscillation ring circuit is generally composed of a number of delay units in series with a NOT gate, and the delay amount of each delay unit and the number of delay units determine the frequency of the output clock signal. Since the digital signal passes through the logic device, redundant jitter will be generated at the moment of level inversion, that is, there is an uncertain amount of jitter between the moment of the actual inversion of the signal level and the moment of ideal inversion, and the number of delay units of the oscillation ring affects the Total jitter of the output clock signal. Generally, the more delay units there are, the greater the amount of jitter, but the lower the frequency of the clock signal.

[0020] The present invention exploits the jitter of such a clock signal as a source of e...

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Abstract

The invention discloses an FPGA-based true random number generator. The FPGA-based true random number generator comprises an oscillating ring circuit, a multi-tap signal delay chain, a trigger array, a logic XOR circuit and a postprocessing circuit. A clock signal generated by the oscillating ring circuit is fed into the signal delay chain, the trigger array samples the level states of all taps of the delay chain under the control of a system clock, acquisition results of all triggers are subjected to logic XOR processing and sent into the postprocessing circuit, and output of the postprocessing circuit is a generated binary true random number sequence. The FPGA-based true random number generator not only can generate random numbers at a rate as high as possible, but also can guarantee the quality of the random numbers.

Description

technical field [0001] The invention belongs to the field of digital circuit design, and in particular relates to an FPGA-based digital circuit design technology. Background technique [0002] True random number generators are important components in modern encrypted communication systems. In addition to the high quality of the generated true random numbers, the rapid development of encrypted communication technologies in recent years, such as quantum key distribution systems, requires true random number generators to be able to generate high-speed random number bit streams in real time. At present, the practical quantum key distribution system has reached 1 to 10Gbps for the generation rate of random number bit stream. The principle of true random number generation is to rely on some uncontrollable physical phenomena (entropy sources) to generate unpredictable random numbers. The upper limit of the random number generation rate is generally determined by the characteristic...

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Application Information

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IPC IPC(8): G06F7/58
CPCG06F7/588
Inventor 王永纲惠聪
Owner UNIV OF SCI & TECH OF CHINA
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