35 results about "Random test generator" patented technology

A validation system is disclosed for validating function of a packet-management unit operationally coupled through a system interface to a processing unit of a processor system. The validation system comprises a user interface for creating an inputting test parameters and test code into the system, a test generator coupled to the user interface, the test generator for generating input packet activity in the form of a packet stream, a model coupled to the test generator for emulating separate and integrated function of the packet management unit, the system interface, and a stream-processing unit and an evaluation software for checking and validating or not validating results. The system validation function relies, in a preferred embodiment, on comparing output results with criteria of the selected test code resulting in an indication of pass or failure of the test. In a preferred embodiment, the system also notifies to cause of failure.

A random number generator has a simple configuration using known inexpensive electronic parts and can generate the tine physical random numbers at a required generator speed. Such a random number generator can provide the true physical random numbers to any sectors of society at dramatically low cost A random pulse generator comprises a thermal noise generating element (2) having a resistor, a conductor or a semiconductor such as a diode adapted to generate thermal noises when no electric current is supplied to them, an analog-amplifier circuit for amplifying the irregular potential generated from the thermal noise generating element and a waveform shaping circuit (6) adapted to take out the output of the amplifier circuit as random rectangular pulse signals. A thermal noise random number generator comprises, in addition to the above components, an n-bit counter (n being an integer) for measuring the dine interval between a random pulse signal output from the waveform shaping circuit (6) and the immediately succeeding random pulse signal and is adapted to output the count of the n-bit counter as natural random number.

In a random number generator, a first converter converts a first analog noise signal into a random digital clock signal and a second converter samples a second analog noise signal asynchronous to the first analog noise signal in response to the random digital clock signal and generates a random digital number stream. In one aspect, a random number generator output block samples the second converter random digital number stream in response to the random digital clock signal and generates a random number generator block output. In another aspect a pseudo noise source state machine generates the random digital clock signal in response to a first seed generated from the first analog noise signal, a second seed from process variation digital amplifier, and a past machine state.

A system includes a tamper detector that includes a linear feedback shift register (LFSR) for generating pseudorandom coded detection signals as a function of seed values and a generator polynomial. The generator polynomial is loaded from a controller to the LFSR via software, and the seed values are directly loaded from a hardware-based random number generator to the LFSR. The tamper detector has output and input elements for connection to ends of a tamper detection circuit, wherein the detection circuit is linked with a physical closure surrounding an electronic circuit. The detection signals are applied to the output element and incoming signals are received from the tamper detection circuit at a comparator via the input element. Comparison of the incoming signals with the coded detection signals is performed to detect interference with the detection circuit in an attempt to tamper with the electronic circuit.

A method of manufacturing a device containing a key is disclosed. The method generally includes the steps of (A) fabricating a chip comprising a random number generator, a nonvolatile memory and a circuit, (B) applying electrical power to the chip to cause the random number generator to generate a signal conveying a sequence of random numbers, (C) commanding the chip to program a first arbitrary value among the random numbers into the nonvolatile memory, wherein the device is configured such that the first arbitrary value as stored in the nonvolatile memory is unreadable from external to the device and (D) packaging the chip.

A method and apparatus are provided for implementing random content of program loops in random test generation for processor verification. A converged branch instruction stream is used by a test generator to ensure that all random conditional branches converge to a main program loop. A built in exception handling mechanism of the test generator enables program interrupts to converge to the main program loop. Mandatory read only registers applied to the test generator allow all register based storage addresses to use registers that maintain a value and thus stabilize the storage address translations through subsequent iterations of the loop. A global class restriction mechanism defines specific restricted instruction classes applied to the test generator avoids inherently problematic operations for the program loops. Machine state detection and restoration mechanisms in the test generator are provided to preserve storage addressability.

A computerized apparatus, method and computer product for generating tests. The apparatus comprises: a processor; an interface for obtaining a test template associated with a computerized system that comprises a template segment comprising instructions and directives or related control constructs; a test generator for generating a test associated with the template segment, comprising: a simulator for determining a state of the system associated with an execution of the test; a selector for selecting a template instruction or segment from the test template based on the state of the system; and a generator configured to generate a multiplicity of instructions based on system's state and on the selected template segment, wherein the test generator further comprises a verifier configured to verify that a previously generated instruction is in line with the current state of the system and with the selected template instruction or segment.

This invention provides an authentication apparatus and an authentication method using a random pulse generator for generating completely random pulses and using a completely random signal as an authentication signal. The authentication apparatus includes: a random pulse generator (hereinafter referred to as the RPG), arranged in a body or a partner side or in both the body and the partner side which generates random pulses; a unit which outputs an authentication signal based on the random pulses generated by the RPG; a unit which stores the authentication signal; a communication unit which transmits / receives an authentication signal; and a control unit which controls the communication of an authentication signal and collate an authentication signal, whereby a complete security can be maintained and safety can be established on the part of the user.

Discloses is a random variation simulation voltage bias signal apparatus in a random number generating device. The apparatus comprises an aggregate logic used for aggregating a state voltage bias signal and a stochastic noise signal to generate a simulation voltage bias signal, and a mechanism used for generating the stochastic noise signal, wherein, the mechanism is coupled with the aggregate logic, and when a random number is allocated in the random number generating device, the stochastic noise signal is varied according to a plurality of logic states of the random number in a bit group.

The present invention provides a pseudo-random code generator based on a generalized information domain, which includes an initial address information (IV) generation module, an IV normalization module, a key generation algorithm (m) module, a constrained processing module, and an encryption module connected in sequence. A key length judging module, the m module is also connected with the activity background generation module at the same time, and the activity background generation module is mainly composed of a physical reconstruction module and a logic reconstruction module. The present invention breaks through the binary limitation of traditional cryptography, introduces the concept of generalized information domain, expands it into a triple structure, realizes the transfer of key security issues to generalized information domain security issues, improves the strength of resistance to cryptanalysis, and further improves information security. confidentiality. The invention can quickly generate very long pseudo-random codes, can increase the size of the key space when used as a key, and can provide specific keys according to different purposes. The generated pseudo-random code has initial value sensitivity and good randomness.

A method and apparatus are provided for implementing automated memory address recording in constrained random test generation for verification of processor hardware designs. A test generation program includes a built in feature to keep track of storage addresses used and to make the addresses available to the test definition. This built in feature of a constrained random test generator allows storage addresses used in the past to be accessed by the current instruction generation eliminating the requirement of deliberately establishing target addresses first. This allows separate test events to interact with the same storage addresses without having to write a special test.