Chip automatic simulation verification system

Abstract

The invention discloses a chip automatic simulation verification system, comprising: a chip system model corresponding to a system-on-chip chip, wherein a hardware model and a software model corresponding to the system-on-chip chip are established; the chip system model randomly generates test vectors and Running the test vector to obtain a test result; the emulator receives and runs a design file corresponding to the SoC; the emulator communicates with the chip system model, receives the test vector and uses the test vector for test verification to obtain a simulation result; The system-on-chip model also compares the test result with the simulation result, if the test result is consistent with the simulation result, then continue to generate the next random test vector, and perform the next round of testing and comparison, otherwise stop the test. A corresponding chip automatic simulation verification method is also disclosed. The above system and method for automatic chip simulation verification are simpler and more efficient during test verification.

Description

technical field [0001] The invention relates to the technical field of detection of chip products, in particular to a chip automatic simulation verification system. Background technique [0002] System On Chip (System On Chip, SOC) refers to the integration of all functional systems required for microelectronic application products on a single chip, which is based on Very Deep Submicron (VDSM) technology and Intellectual Property (IP) ) nuclear multiplexing technology as the support. SOC technology is the current development trend of Very Large Scale Integrate (VLSI), and it is also the main technology and method to solve Time to Market (TTM) in the development of electronic products. [0003] With the rapid development of deep submicron technology, the integration scale of chips is getting larger and larger, and the verification of chip functions has become more and more important and complex and time-consuming, and the design methods of chips have also undergone tremendou...

AI Technical Summary

Problems solved by technology

However, the traditional chip simulation verification takes a long time, the degree of automation is low, and it is time-consuming and laborious, which leads to a longer development cycle of the entire chip.

[0004] The traditional verification test mode is open-loop, requiring special personnel to manage and control input test vectors and observe simulation waveforms, which is time-consuming and labor-intensive

[0005] However, some automatic simulation platforms, such as the PLI automatic simulation platform, also have various problems. 1) The PLI standard is complicated to use; 2) PLI must define system tasks or functions, and associate the calltf C function with the system task / function name; 3) The communication protocol interaction between the C model and the circuit is complex

This results in a high barrier to entry for using these automated emulation platforms

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