57results about "Pulse generation with predetermined statistical distribution" patented technology

An embodiment of an IC is provided. The IC includes a memory, a controller, an intrusion detector and a memory clear circuit. The memory is configured to store sensitive data. The controller is configured to access the memory. The intrusion detector is configured to detect whether an intrusion event is present in response to an input signal. The memory clear circuit is configured to clear the sensitive data of the memory when the intrusion detector detects the intrusion event.

The invention discloses a random analog pulse signal generation circuit, which is characterized in that the output of an excitation pulse generation module obeying discrete random time distribution is connected to an excitation pulse generation module obeying continuous random time distribution, and the excitation pulse generation module is used for generating square wave pulses of which the time interval of the front edges of two adjacent excitation square waves obeying discrete distribution; the output of the excitation pulse generation module obeying continuous random time distribution is connected to the analog narrow pulse generation module, and the analog narrow pulse generation module is used for converting the generated square-wave pulse into a square-wave excitation pulse of which the leading edge obeys specific distribution; and the analog narrow pulse generation module is used for converting the leading edge of the square wave excitation pulse into a narrow pulse signal so as to generate a signal waveform suitable for a fast detector electronics system test. According to the circuit, the inherent discreteness of digital logic is eliminated while better programmability of the digital logic is kept, so that the finally output pulse waveform signal is closer to the time characteristic of the signal processed by the detector under the real working condition.

Provided is a semiconductor integrated circuit device including a pseudo-random pattern generator configured to output a pseudo-random pattern, a terminal for externally outputting an output of the pseudo-random pattern generator or an evaluation result of noise tolerance evaluated on the basis of the pseudo-random pattern.

This specification provides a method and related equipment for calculating obfuscated circuits. It is applied to a first computing device corresponding to the obfuscated circuit executor, which holds first input data corresponding to a first logic gate included in the obfuscated circuit. A second computing device corresponding to the obfuscated circuit generator holds expected first and second output data corresponding to the first logic gate. The first input data is 0 or 1. The method includes: obtaining a random number i and its corresponding random value r generated by running a randomized unintended transmission protocol. i The random number i is 0 or 1; obtain the intermediate calculation result calculated by the second computing device based on the first random value, the second random value, the first output data, and the second output data; if the value of the first input data is 0, based on the random value r i Calculate the obfuscation value corresponding to the first output data; if the first input data is 1, then based on the random value r... i The intermediate calculation result f is used to calculate the obfuscation value corresponding to the second output data.

A hardware boot circuit includes a random number generator circuit (103) configured to generate random values, a reference clock circuit (107) configured to generate a reference clock signal (127) that includes a series of intervals of fixed size, a clock gate circuit (102) configured to switch off at least one clock pulse in each interval to generate a randomized clock signal (122) at a root node of a clock network, and a boot core circuit (104) configured to use the randomized clock signal (122) to access an internal memory storing boot instructions. Clock pulses that are switched off are randomized by the random values from the random number generator (103). The randomized clock signal (122) or additional randomized clock signals (123, 124) generated by the clock gate circuit (102) may be used to clock peripherals (108) and / or processors (110) of a digital electronic device (100) that includes the hardware boot circuit. The random number generator (103) may include a physical entropy source.

The application belongs to the technical field of random number generation, and particularly relates to a random signal generation device based on a saturable absorber semiconductor laser. The device comprises a random self-pulsation entropy source, a photodetector and a pulse amplitude quantization module. The random self-pulsation entropy source adopts a saturable absorber semiconductor laser (preferably a DFB-SA structure), generates optical pulses with random amplitudes and stable repetition periods by injecting a driving current in a gain region and applying a reverse bias voltage in an absorption region; the photodetector adopts a PIN photodiode or an avalanche photodiode to convert the optical pulses into corresponding electrical pulses; and the pulse amplitude quantization module comprises a differential comparator and a peak detection circuit, which quantizes the peak value of the electrical pulses in each pulse period by using a fixed threshold or an adaptive threshold to generate a random bit sequence. The application realizes high-speed and high-stability random signal generation without an external electric clock, an ADC and digital post-processing, and has a simple device structure, low power consumption and high integration.

This invention relates to a device for generating truly random numbers, comprising a digital chaotic oscillating autonomous Boolean network as an entropy source. According to the invention, the proposed digital chaotic oscillating autonomous Boolean network comprises three interconnected logic elements, two of which represent two-input XOR gates and / or XNOR gates, while the third logic element has three inputs and one output, and implements a logic "one-to-one counting" function, wherein if a logic 1 appears at no more than one input of the third logic element, the output of the third logic element is set to logic 1; otherwise, the output is set to logic 0. The resulting technical advantages include improved truly random number generation speed while reducing energy consumption.

The present disclosure provides a clock circuit and related method improving frequency hopping. The clock circuit may comprise a frequency divider and a frequency hopping circuit. The frequency divider may perform a frequency division according to a first divisor number. When hopping to a frequency or a spread spectrum range which is corresponding to an input number, if a convergence condition is not satisfied, the frequency hopping circuit may perform a stepping operation to update the first divisor number from a previous value to a current value which may not equal the input number.

A semiconductor device includes a pulse input circuit including flip-flops constituting each of two front-stage counters having different holding states from each other and configured such that first pulses from an even-stage ring circuit are input to each of the two front-stage counters, an edge detection circuit configured to detect edges of outputs of the two front-stage counters and output a second pulse having a predetermined pulse width larger than a predetermined value based on the edge, and a counter circuit including a rear-stage counter to which the second pulse is input. The edge detection circuit is configured to output the second pulse or a stepwise signal when a pulse width of the first pulse is smaller than the predetermined value.

Embodiments include methods performed by an apparatus configured to generate output signals for transmission. Such methods include detecting a triggering condition related to a change in operational status of the apparatus and selecting one of a plurality of pre-shaping vectors based on the triggering condition and past operating conditions of the apparatus during a plurality of most recent time intervals. Each pre-shaping vector includes a plurality of values that compensate for effects of voltage variation of a power supply for the apparatus. Such methods include, during a plurality of time intervals after the triggering condition, applying the values of the selected pre-shaping vector to respective information-carrying signals, thereby generating pre-shaped information-carrying signals. Such methods include generating output signals for transmission during the plurality of subsequent time intervals, using the pre-shaped information-carrying signals. The output signals are generated by an active circuit powered by the power supply.

This invention belongs to the field of electronic circuit technology, specifically relating to a true random number generation device based on a carbon-based chip, comprising: a broadband optical noise entropy source and an entropy collector. The broadband noise entropy source is used to generate a broadband chaotic noise signal. The entropy collector includes: a sample-and-hold circuit; a TIQ comparator for converting the sampling result into a digital signal output; a one-hot code generator for converting the digital signal output by the TIQ comparator into a one-hot code; and an encoder for converting the one-hot code into a binary code. In this invention, all parts of the entropy collector are designed using CNTFET technology, reducing power consumption.

The invention relates to a method for generating a random number comprising the following steps: a first input signal (I(t)) is generated, which changes randomly over time (t); a second input signal (I(t+Δt)) is generated, which also changes randomly over time; the first input signal (I(t)) is compared with the second input signal (I(t+Δt); depending on the result of the comparison, either a first logical 0 or a first logical 1 is generated, thus generating a first bit of a binary random number; after generating the first bit of the binary random number, the steps are repeated multiple times to generate further bits of the binary random number. The invention further relates to a random number generator for generating a random number according to the claimed method, comprising a memristor and a measuring device for reading a resistance value of the memristor to generate an input signal (I(t)) that changes randomly over time.The random number generator comprises a delay device (2) that delays the generated input signal (I(t)), a comparator (1) that compares the input signal I(t) with the time-delayed input signal (I(t+Δt)) and generates bits of a first random number according to a first frequency by comparison. The random number generator comprises a first processing device (3) that converts bits of the first generated random number according to a second frequency (CLK 1) into bits of a second random number, and a second processing device (4) that converts bits of the second generated random number according to a third frequency (CLK 2) into bits of a third random number. The first frequency is lower than the second frequency (CLK 1). The second frequency (CLK 1) is lower than the third frequency (CLK 2).

The invention relates to a device for spread spectrum clock generation. A multiplexer includes a plurality of inputs, outputs, and a plurality of terminals. The plurality of inputs receive a set of clocks from a plurality of signal lines. One of the signal lines is a distributed signal line. The allocated signal lines transmit an input clock to the multiplexer. The output routes the input clock onto a clock line. One of the clocks is the input clock. The plurality of terminals receive control bits from a plurality of select lines. The multiplexer selects the allocated signal line from the signal lines according to a binary value of the control bit. The binary value of the control bit is adjusted during successive time slots.

To provide a true random number generator for realizing information encryption by generating a random bit by a stochastic switching operation through a feedback loop phenomenon in a channel region of a gate diode, and controlling a generation probability of the random bit through control of voltage application.SOLUTION: The true random number generator 300 includes a gated diode 301 and a control transistor 302. The gated diode includes a p + - i-n + diode structure disposed between a drain and a source, a gate oxide layer disposed on an intrinsic region of the p + - i-n + diode structure, and a first gate and a second gate disposed on the gate oxide layer. The control transistor includes a control drain terminal connected to the source, a control gate terminal, and a control source terminal, and controls electron injection into the p + - i-n + diode structure by controlling a gate voltage applied through the control gate terminal.SELECTED DRAWING: Figure 3A

Electronic devices, circuitry, and methods are provided to efficiently generate a dither signal. An electronic device may include an output device, such as a speaker, to output a media signal, such as an audio signal, based on dithered media data, such as dithered audio data. The electronic device may include dithering circuitry to generate a dither signal, based on a first pseudorandom signal from a first linear feedback shift register and a second pseudorandom signal from a second linear feedback shift register, to add to the media signal to generate the dithered media signal.

A method comprises: producing, using a first metastable circuit, a bistable state that varies over time between a first stable voltage and a second stable voltage, where a fraction of time that the bistable state spends at the first stable voltage is associated with a first probability; producing, using a first noise circuit, a first voltage distribution; producing, using a second noise circuit, a second voltage distribution; and producing, using a first mixer circuit, a third voltage distribution that is based at least in part on the bistable state, the first voltage distribution, and the second voltage distribution.

True random number generators including Fibonacci-Galois ring oscillators with a stochastic start-up condition are described. An example ring oscillator circuit includes a first oscillating loop comprising at least three inverter stages, where the first oscillating loop is configured to provide a start-up stochastic condition for starting oscillations in a second oscillating loop. The second oscillating loop comprises a chain of inverter stages and a plurality of switches whose state is determined by a feedback polynomial. The ring oscillator circuit is to: (1) during a first mode of operation, enable oscillations in the first oscillating loop while keeping the second oscillating loop open, and thereby generate the stochastic start-up condition for starting oscillations in the second oscillating loop, and (2) during a second mode of operation, enable oscillations in the second oscillating loop in response to the stochastic start-up condition, while keeping the first oscillating loop open.

The application provides a random number generator and a random number generation method based on a three-edge ring oscillator, which can be applied to the technical field of random number generation. The random number generator comprises a three-edge ring oscillator module configured to start an oscillation mode under the control of a control signal and output an oscillation signal in the oscillation mode; an entropy extraction module configured to extract original bits and an effective indication signal based on the oscillation signal; a detection module configured to detect the state of the oscillation signal and output a collapse signal to a control module in the case that the state of the oscillation signal represents that a collapse event occurs in the oscillation signal; the control module is configured to output the control signal to the three-edge ring oscillator module and control the three-edge ring oscillator module to restart the oscillation mode in the case that the collapse signal is received, store the original bits and obtain an original bit sequence; and a conversion module configured to convert the original bit sequence into a target random number.

The invention provides a double-random jitter frequency circuit and method, and the circuit comprises a pseudo-random signal generation module which is used for generating two paths of pseudo-random control signals; a triangular wave generation module; the cooperative modulation module is connected between the pseudo-random signal generation module and the triangular wave generation module and is used for dynamically modulating at least one working parameter of the triangular wave generation module according to the pseudo-random control signal, so that the time domain characteristic of the digital control signal output by the triangular wave generation module has periodicity and randomness; and the mixing and frequency control module is used for generating a mixing control signal according to the pseudo-random control signal and the digital control signal, and controlling the frequency of the oscillator to randomly change within a preset range so as to generate a jittering frequency clock signal. According to the invention, triangular wave modulation and random modulation are organically combined to form a cooperative modulation mechanism, periodicity of triangular wave jitter frequency and uncertainty of random jitter frequency are avoided, and an excellent EMI suppression effect can be provided for a vehicle gauge level DC-DC chip to the greatest extent.

Random number generator (GL) comprising adjustable speed ring oscillators (GPRS, GPRS'), which have outputs (o-GPRS, o-GPRS') connected to inputs (i1-UM, i2-UM) of a metastability circuit (UM) and inputs (i1-DF, i2-DF) of a phase detector (DF), which outputs (o-UM, o-DF) are connected to inputs (r-US', i-US') of a control circuit (US'), having output (o-US') connected to control inputs (s-GPRS, s-GPRS') of the adjustable speed ring oscillators (GPRS, GPRS'). The outputs (o-UM, o-DF) of the metastability circuit (UM) and the phase detector (DF) are being outputs (o-GL, o2-GL) of the random number generator (GL).

A system and method for random number generation. The method includes receiving, at a first single-photon avalanche diode (SPAD), a first series of photons, converting, by the first SPAD, the first series of photons into a first series of electrical pulses comprising a first random time interval between each pulse of the first series of electrical pulses, and outputting, by an output circuit in communication with the first SPAD, a random binary stream based at least in part on the first series of electrical pulses. A system is provided for generating random numbers including one or more SPADs, one or more associated quenching circuits, and output electronics configured to adjust thresholds, combine signals generated by an array of SPADS, condition signals, and output a stream of generated random numbers.

The invention relates to a method for generating a random number comprising the following steps: A first input signal (I(t)) is generated, which changes randomly over time (t). a second input signal (I(t+Δt) is generated, which changes randomly over time, the first input signal (I(t)) is compared with the second input signal (I(t+Δt), Depending on the result of the comparison, either a first logical 0 or generates a first logical 1, thus creating the first bit of a binary random number. After generating the first bit of the binary random number, the steps are repeated several times to generate further bits of the binary random number. The invention further relates to a random number generator for generating a random number according to the claimed method, comprising a memristor and a measuring device for reading a resistance value of the memristor to generate an input signal (I(t)) that changes randomly over time. The random number generator includes a delay device (2) that delays the generated input signal (I(t)) in time, a comparator (1) that compares the input signal I(t)) with the time-delayed input signal (I(t+Δt)) and that generates bits of a first random number according to a first frequency by comparison.The random number generator comprises a first processing unit (3) that converts bits of the first generated random number into bits of a second random number according to a second frequency (CLK 1), and a second processing unit (4) that converts bits of the second generated random number into bits of a third random number according to a third frequency (CLK 2). The first frequency is lower than the second frequency (CLK 1). The second frequency (CLK 1) is lower than the third frequency (CLK 2).

The application relates to the field of laser technology and discloses a parallel random signal generation device and method based on self-pulsation. The device comprises a multimode optical pulse entropy source module, a wavelength division demultiplexing module, an optical-electric conversion module and a peak value judgment module. The multimode optical pulse entropy source module is used for generating a self-pulsation optical pulse sequence with random amplitude and period stability; the wavelength division demultiplexing module is used for separating the self-pulsation optical pulse sequence into multiple optical channels independent of each other according to wavelength differences; the optical-electric conversion module is used for converting the optical pulse sequence in each optical channel into a corresponding electric pulse signal; and the peak value judgment module is used for judging the electric pulse signal once in each optical pulse repetition period and outputting discrete random bits. The application effectively avoids the problems that high-speed electric sampling depends on an external clock, which can cause large sampling jitter, complex system structure and difficulty in integration.

Random sequence generators utilizing one or more noise generators that include an inverter chain with at least one input stage inverter configured with resistive feedback and additional inverters configured in series with the at least one input stage inverter, wherein an output of the inverter chain is coupled to a bit sequence generator.

True random number generators including Fibonacci-Galois ring oscillators with a stochastic start-up condition are described. An example ring oscillator circuit includes a first oscillating loop comprising at least three inverter stages, where the first oscillating loop is configured to provide a start-up stochastic condition for starting oscillations in a second oscillating loop. The second oscillating loop comprises a chain of inverter stages and a plurality of switches whose state is determined by a feedback polynomial. The ring oscillator circuit is to: (1) during a first mode of operation, enable oscillations in the first oscillating loop while keeping the second oscillating loop open, and thereby generate the stochastic start-up condition for starting oscillations in the second oscillating loop, and (2) during a second mode of operation, enable oscillations in the second oscillating loop in response to the stochastic start-up condition, while keeping the first oscillating loop open.

A hardware boot circuit includes a random number generator circuit configured to generate random values, a reference clock circuit configured to generate a reference clock signal that includes a series of intervals of fixed size, a clock gate circuit configured to switch off at least one clock pulse in each interval to generate a randomized clock signal at a root node of a clock network, and a boot core circuit configured to use the randomized clock signal to access an internal memory storing boot instructions. Clock pulses that are switched off are randomized by the random values from the random number generator. The randomized clock signal or additional randomized clock signals generated by the clock gate circuit may be used to clock peripherals and / or processors of a digital electronic device that includes the hardware boot circuit. The random number generator may include a physical entropy source.