13results about "Pulse generation with predetermined statistical distribution" patented technology

Provided is a semiconductor integrated circuit device including a pseudo-random pattern generator configured to output a pseudo-random pattern, a terminal for externally outputting an output of the pseudo-random pattern generator or an evaluation result of noise tolerance evaluated on the basis of the pseudo-random pattern.

The application belongs to the technical field of random number generation, and particularly relates to a random signal generation device based on a saturable absorber semiconductor laser. The device comprises a random self-pulsation entropy source, a photodetector and a pulse amplitude quantization module. The random self-pulsation entropy source adopts a saturable absorber semiconductor laser (preferably a DFB-SA structure), generates optical pulses with random amplitudes and stable repetition periods by injecting a driving current in a gain region and applying a reverse bias voltage in an absorption region; the photodetector adopts a PIN photodiode or an avalanche photodiode to convert the optical pulses into corresponding electrical pulses; and the pulse amplitude quantization module comprises a differential comparator and a peak detection circuit, which quantizes the peak value of the electrical pulses in each pulse period by using a fixed threshold or an adaptive threshold to generate a random bit sequence. The application realizes high-speed and high-stability random signal generation without an external electric clock, an ADC and digital post-processing, and has a simple device structure, low power consumption and high integration.

True random number generators including Fibonacci-Galois ring oscillators with a stochastic start-up condition are described. An example ring oscillator circuit includes a first oscillating loop comprising at least three inverter stages, where the first oscillating loop is configured to provide a start-up stochastic condition for starting oscillations in a second oscillating loop. The second oscillating loop comprises a chain of inverter stages and a plurality of switches whose state is determined by a feedback polynomial. The ring oscillator circuit is to: (1) during a first mode of operation, enable oscillations in the first oscillating loop while keeping the second oscillating loop open, and thereby generate the stochastic start-up condition for starting oscillations in the second oscillating loop, and (2) during a second mode of operation, enable oscillations in the second oscillating loop in response to the stochastic start-up condition, while keeping the first oscillating loop open.

The application provides a random number generator and a random number generation method based on a three-edge ring oscillator, which can be applied to the technical field of random number generation. The random number generator comprises a three-edge ring oscillator module configured to start an oscillation mode under the control of a control signal and output an oscillation signal in the oscillation mode; an entropy extraction module configured to extract original bits and an effective indication signal based on the oscillation signal; a detection module configured to detect the state of the oscillation signal and output a collapse signal to a control module in the case that the state of the oscillation signal represents that a collapse event occurs in the oscillation signal; the control module is configured to output the control signal to the three-edge ring oscillator module and control the three-edge ring oscillator module to restart the oscillation mode in the case that the collapse signal is received, store the original bits and obtain an original bit sequence; and a conversion module configured to convert the original bit sequence into a target random number.

The application relates to the field of laser technology and discloses a parallel random signal generation device and method based on self-pulsation. The device comprises a multimode optical pulse entropy source module, a wavelength division demultiplexing module, an optical-electric conversion module and a peak value judgment module. The multimode optical pulse entropy source module is used for generating a self-pulsation optical pulse sequence with random amplitude and period stability; the wavelength division demultiplexing module is used for separating the self-pulsation optical pulse sequence into multiple optical channels independent of each other according to wavelength differences; the optical-electric conversion module is used for converting the optical pulse sequence in each optical channel into a corresponding electric pulse signal; and the peak value judgment module is used for judging the electric pulse signal once in each optical pulse repetition period and outputting discrete random bits. The application effectively avoids the problems that high-speed electric sampling depends on an external clock, which can cause large sampling jitter, complex system structure and difficulty in integration.

True random number generators including Fibonacci-Galois ring oscillators with a stochastic start-up condition are described. An example ring oscillator circuit includes a first oscillating loop comprising at least three inverter stages, where the first oscillating loop is configured to provide a start-up stochastic condition for starting oscillations in a second oscillating loop. The second oscillating loop comprises a chain of inverter stages and a plurality of switches whose state is determined by a feedback polynomial. The ring oscillator circuit is to: (1) during a first mode of operation, enable oscillations in the first oscillating loop while keeping the second oscillating loop open, and thereby generate the stochastic start-up condition for starting oscillations in the second oscillating loop, and (2) during a second mode of operation, enable oscillations in the second oscillating loop in response to the stochastic start-up condition, while keeping the first oscillating loop open.

Embodiments of the present disclosure relate to the field of phase-locked loops technology, and disclose a phase-locked loop, a radar system and a method for randomizing initial phases of FMCW signals. The phase-locked loop includes a phase-locked loop circuit (100) and a stochastic control signal generator (200). In response to a respective clock signal of the plurality of clock signals indicating a respective target moment of one or more target moments, the stochastic control signal generator (200) inputs a stochastic control signal to the phase-locked loop circuit (100), so that the accumulated value of the plurality of fractional frequency division values of the phase-locked loop circuit (100) is converted into a random value, and that a plurality of initial phase differences respectively corresponding to the plurality of chirp signals output by the phase-locked loop circuit (100) form a non-arithmetic sequence. A plurality of pieces of velocity information resulting from the spurious signals are distributed over different velocity dimensions. In this way, a strength of the spurious signals on individual velocity dimension can be decreased, and the two false targets having fixed velocities can be prevented from occurring, thereby improving the detection accuracy of the radar system. Moreover, the plurality of chirp signals can have random phases, thereby improving the anti-interference ability of the radar system.

Random number generator (GL) comprises three ring oscillators (GP1, GP2, GP3) and seven bistables (UB1, UB2, UB3, UB4, UB5, UB6, UB7). The ring oscillators (GP1, GP2, GP3) comprise delay lines (LO1, LO2, LO3) closed in loops. The delay lines (LO1, LO2, LO3) comprise delays (EO) connected in series between inputs (i-LO1, i- LO2, i-LO3) and outputs (o-LOl, O-L02, O-L03) of the delay lines. Outputs (o-UB1, o-UB2, o-UB3, o-UB4, o-UB5, 0-UB6, o-UB7) of the bistables (UB1, UB2, UB3, UB4, UB5, UB6, UB7) are connected to outputs (o1-GL, o2-GL, o3-GL, o4-GL, o-5GL, 06-GL, o7-GL) of the random number generator (GL). Inputs (i1-UB1, i2-UB1, i1-UB2, i2- UB2, i1-UB3, i2-UB3, i1-UB4, i2-UB4, i1-UB5, i2-UB5, i1-UB6, i2- UB6, i1-UB7, i2-UB7) of the bistables (UB1, UB2, UB3, UB4, UB5, UB6, UB7) are connected to the delay lines (LO1, LO2, LO3) of the ring oscillators (GP1, GP2, GP3) to outputs of selected delays (EO).

An integrated circuit includes signal-source circuitry (SSC), an SSC power supply circuit (SSC-PS) and a digitization circuit. The SSC is configured to generate an output signal, which is guaranteed to meet specified electrical parameters provided that a supply voltage to the SSC is within a specified operating voltage range. The SSC-PS is configured to power the SSC with a reduced voltage that is below the specified operating voltage range, thereby causing the output signal to be noisy. The digitization circuit is configured to digitize the noisy output signal so as to generate a respective sequence of random numbers.