113results about "Pulse generation with predetermined statistical distribution" patented technology

A programmable driver circuit (54) and related method (600) for simultaneously controlling multiple tunable probabilistic bit generators are disclosed. The driver circuit comprises a plurality of programmable voltage generators (52; 30), a programming unit (35) and a non-volatile memory unit (34a-b). Input terminals of the plurality of programmable voltage generators are jointly connectible to a single voltage supply source. The programming unit is configured to generate a sequence of programming pulses for the different voltage generators. Each voltage generator comprises a single-stage or multi-stage voltage divider circuit (31) formed by a series of resistive elements (32-1; 32-2; 33). The non-volatile memory unit (34a-b) comprises at least the resistive element positioned first in the series of resistive elements as a programmable resistance and a program control transistor (34-1) connected in series between the programmable resistance and a fixed reference voltage. A control gate of the program control transistor is operatively coupled to the programming unit to receive the sequence of programming pulses for the programmable voltage generator when operated in a programming mode.

An embodiment of an IC is provided. The IC includes a memory, a controller, an intrusion detector and a memory clear circuit. The memory is configured to store sensitive data. The controller is configured to access the memory. The intrusion detector is configured to detect whether an intrusion event is present in response to an input signal. The memory clear circuit is configured to clear the sensitive data of the memory when the intrusion detector detects the intrusion event.

Provided is a reconfigurable Ring Oscillator (RO) Physical Unclonable Function (PUF), which comprises a NAND gate with a first input line and a second input line and a series of inverters with at least one memory cell placed between two inverters of the series of inverters, where an output of a last inverter provides input to the second input line, and where the memory cell comprises a Field Effect Transistor (FET). In addition, the reconfigurable RO PUF comprises a frequency counter, where the output of the last inverter provides input to the frequency counter. In normal operation mode, the first input line is on to enable ring oscillation and the FET is off. In reconfiguration mode, the first input line is off and the FET is on to enable reconfiguration.

The invention discloses a random analog pulse signal generation circuit, which is characterized in that the output of an excitation pulse generation module obeying discrete random time distribution is connected to an excitation pulse generation module obeying continuous random time distribution, and the excitation pulse generation module is used for generating square wave pulses of which the time interval of the front edges of two adjacent excitation square waves obeying discrete distribution; the output of the excitation pulse generation module obeying continuous random time distribution is connected to the analog narrow pulse generation module, and the analog narrow pulse generation module is used for converting the generated square-wave pulse into a square-wave excitation pulse of which the leading edge obeys specific distribution; and the analog narrow pulse generation module is used for converting the leading edge of the square wave excitation pulse into a narrow pulse signal so as to generate a signal waveform suitable for a fast detector electronics system test. According to the circuit, the inherent discreteness of digital logic is eliminated while better programmability of the digital logic is kept, so that the finally output pulse waveform signal is closer to the time characteristic of the signal processed by the detector under the real working condition.

A voltage divider for generating probabilistic bits (p-bits) through stochastic magnetic tunnel junction devices (sMTJs). The voltage divider comprises a first and a second sMTJ, each including a first and a second magnet separated by an insulator. A positive DC voltage (VDD) is connected to the first electrical terminal of the first sMTJ, while a negative DC voltage (VSS) is connected to the second electrical terminal of the second sMTJ. The p-bits randomly oscillate between resistance states in response to thermal noise. The voltage divider also includes a comparator with a non-inverting input, an inverting input connected to the p-bit output, a source, a drain, and an output terminal. The output voltage (Vout) at the comparator is determined based on the resistances of the sMTJs.

A digital-to-analog converter (DAC) circuit, an electronic device including the digital-to-analog converter circuit, and a control method of the digital-to-analog converter circuit are provided. The DAC circuit includes: a serializer circuit including a plurality of multiplexers and configured to convert a parallel code in digital form into a serial code using the plurality of multiplexers; and a cell array including a plurality of unit cells and configured to output an analog signal based on the serial code. The serializer circuit includes: a pseudo-random number generation circuit configured to generate a random number in response to an edge of a first clock signal; a first switching circuit connected to the first multiplexer; a second switching circuit connected to the second multiplexer; and a random number circuit configured to transmit different random numbers generated by the pseudo-random number generation circuit in response to different edges of the first clock signal to the first switching circuit and the second switching circuit, respectively.

An apparatus and method for implementing a probabilistic bit (p-bit) circuit with enhanced tunability is disclosed. The apparatus includes multiple magnetic tunnel junctions (MTJs) connected in series to a drain of a transistor. The apparatus also includes a resistor connected to a source of the transistor. The resistor is of a resistance value that is selected based on an average equivalent resistance value of a series combination of the multiple MTJs. The apparatus includes a comparator configured to receive voltage from the drain (“drain voltage”) and generate an output voltage based on a reference voltage and the drain voltage. The method includes generating, using a first circuitry, a drain voltage that is fluctuating over time, and generating, using a second circuitry, an output voltage that is varying continuously over time by comparing the fluctuating voltage with a reference voltage.

Provided is a semiconductor integrated circuit device including a pseudo-random pattern generator configured to output a pseudo-random pattern, a terminal for externally outputting an output of the pseudo-random pattern generator or an evaluation result of noise tolerance evaluated on the basis of the pseudo-random pattern.

This specification provides a method and related equipment for calculating obfuscated circuits. It is applied to a first computing device corresponding to the obfuscated circuit executor, which holds first input data corresponding to a first logic gate included in the obfuscated circuit. A second computing device corresponding to the obfuscated circuit generator holds expected first and second output data corresponding to the first logic gate. The first input data is 0 or 1. The method includes: obtaining a random number i and its corresponding random value r generated by running a randomized unintended transmission protocol. i The random number i is 0 or 1; obtain the intermediate calculation result calculated by the second computing device based on the first random value, the second random value, the first output data, and the second output data; if the value of the first input data is 0, based on the random value r i Calculate the obfuscation value corresponding to the first output data; if the first input data is 1, then based on the random value r... i The intermediate calculation result f is used to calculate the obfuscation value corresponding to the second output data.

A hardware boot circuit includes a random number generator circuit (103) configured to generate random values, a reference clock circuit (107) configured to generate a reference clock signal (127) that includes a series of intervals of fixed size, a clock gate circuit (102) configured to switch off at least one clock pulse in each interval to generate a randomized clock signal (122) at a root node of a clock network, and a boot core circuit (104) configured to use the randomized clock signal (122) to access an internal memory storing boot instructions. Clock pulses that are switched off are randomized by the random values from the random number generator (103). The randomized clock signal (122) or additional randomized clock signals (123, 124) generated by the clock gate circuit (102) may be used to clock peripherals (108) and / or processors (110) of a digital electronic device (100) that includes the hardware boot circuit. The random number generator (103) may include a physical entropy source.

A semiconductor device supplies power to an encryption circuit. The semiconductor device comprises a voltage generator including a series regulator and a shunt regulator, and a controller configured to randomly switch the shunt regulator between an ON state and an OFF state.

The present invention discloses a method for generating a pseudo-random sequence for integer data in signal processing. The seed can be arbitrarily selected within the range of integer data. The sequence iteration algorithm does not use multiplication and modulo operations, and the sequence data traverses the entire data range. The present invention simplifies the linear congruence algorithm, making the generation speed of the pseudo-random sequence faster and more resource-saving, while still retaining the characteristic of a long output sequence period. The present invention is applicable to various integer data types and can also be extended to any hexadecimal data with the number of bits n≥8. Pseudo-random sequences play an important role in information security fields such as multiple access communication, encryption algorithms, data scrambling, signal synchronization, error code testing, security protocols, digital watermarking, and cryptographic chips.

A device for forming a broadband pseudo-random noise signal, comprising: a group of channels, each channel including a PRN code generator and an NCO with controlled frequency and phase, the NCO generating a gating pulse output to the PRN code generator. The PRN code generator forms a new +1 or -1 sequence element according to the gating pulse. The device also includes: a first modulator, the first modulator having a plurality of weight coefficients; a plurality of multipliers, each multiplied by one of the weight coefficients; an adder, the adder outputting the sum of the output signals of the plurality of multipliers; and a mixer having an orthogonal output signal, the mixer multiplies the output of the adder by a sine of a low intermediate frequency and the output of the adder by a cosine of a low intermediate frequency. The device also includes: a processor, the processor controlling a group of channels; a transceiver module, the transceiver module for receiving an orthogonal signal and / or transmitting an orthogonal signal; and an interface, the interface connecting the output of the mixer to the transceiver module.

The application belongs to the technical field of random number generation, and particularly relates to a random signal generation device based on a saturable absorber semiconductor laser. The device comprises a random self-pulsation entropy source, a photodetector and a pulse amplitude quantization module. The random self-pulsation entropy source adopts a saturable absorber semiconductor laser (preferably a DFB-SA structure), generates optical pulses with random amplitudes and stable repetition periods by injecting a driving current in a gain region and applying a reverse bias voltage in an absorption region; the photodetector adopts a PIN photodiode or an avalanche photodiode to convert the optical pulses into corresponding electrical pulses; and the pulse amplitude quantization module comprises a differential comparator and a peak detection circuit, which quantizes the peak value of the electrical pulses in each pulse period by using a fixed threshold or an adaptive threshold to generate a random bit sequence. The application realizes high-speed and high-stability random signal generation without an external electric clock, an ADC and digital post-processing, and has a simple device structure, low power consumption and high integration.

Two defense mechanisms, a hardware-based and software-based solution, are provided to protect a device during charging. The defenses randomly perturb the current drawn during charging thereby masking the unique patterns of the user's activities. It is shown that the two defenses force each one of the attacks to perform no better than random guessing, thus acting as effective defense mechanisms against all such types of attacks.

A fluctuation oscillator (1) is provided with: an adder (11) that has an input terminal (111) into which inputted is an input signal (S1) including a main signal and an uncorrelated signal which is uncorrelated to the main signal and has a higher frequency than the main signal, and that adds a feedback signal (S5) to the input signal (S1); a threshold value discrimination unit (12) for generating a pulse signal (S3) by comparing, against a threshold value, an addition signal (S2) obtained by addition by the adder (11); a transient response unit (13) for causing transient response of the generated pulse signal (S3) and generating an output signal (S4); and a feedback loop (16) for feeding back the output signal (S4) to the adder (11) as the feedback signal (S5).

The present description relates to a random number generation circuit (2) of the type of correlated sampling ring oscillator comprising: two identical ring oscillators (RO1, RO2) implemented in CMOS technology on FDSOI; a circuit (104) sampling and storing an output (O1) of one of the two oscillators (RO1) at a frequency of the other of the two oscillators (RO2) and providing a corresponding binary signal (Beat); and a circuit (200) driving back gates of PMOS and NMOS transistors of at least one delay element of at least one of the two oscillators (RO1, RO2) from a period difference between the two oscillators (RO1, RO2).

This invention relates to a device for generating truly random numbers, comprising a digital chaotic oscillating autonomous Boolean network as an entropy source. According to the invention, the proposed digital chaotic oscillating autonomous Boolean network comprises three interconnected logic elements, two of which represent two-input XOR gates and / or XNOR gates, while the third logic element has three inputs and one output, and implements a logic "one-to-one counting" function, wherein if a logic 1 appears at no more than one input of the third logic element, the output of the third logic element is set to logic 1; otherwise, the output is set to logic 0. The resulting technical advantages include improved truly random number generation speed while reducing energy consumption.

Embodiments of the present invention provide an oscillator, a random number generator, and a method for operating the oscillator. The oscillator circuit includes a plurality of inverters connected in a series, at least a first feedback tap and a second feedback tap, and an alternating circuit. The at least first feedback tap and the second feedback tap are configured to respectively feedback a first output signal and a second output signal, the first output signal and the second output signal being derived from a first point and a second point in the series, respectively. The alternating circuit is configured to derive an input signal from the at least first output signal and the second output signal by alternating between the at least first feedback tap and the second feedback tap, and apply the input signal to the input of the series.

The present disclosure provides a clock circuit and related method improving frequency hopping. The clock circuit may comprise a frequency divider and a frequency hopping circuit. The frequency divider may perform a frequency division according to a first divisor number. When hopping to a frequency or a spread spectrum range which is corresponding to an input number, if a convergence condition is not satisfied, the frequency hopping circuit may perform a stepping operation to update the first divisor number from a previous value to a current value which may not equal the input number.

A semiconductor device includes a pulse input circuit including flip-flops constituting each of two front-stage counters having different holding states from each other and configured such that first pulses from an even-stage ring circuit are input to each of the two front-stage counters, an edge detection circuit configured to detect edges of outputs of the two front-stage counters and output a second pulse having a predetermined pulse width larger than a predetermined value based on the edge, and a counter circuit including a rear-stage counter to which the second pulse is input. The edge detection circuit is configured to output the second pulse or a stepwise signal when a pulse width of the first pulse is smaller than the predetermined value.

An apparatus for forming wideband pseudo random noise signals includes a set of channels each comprising an NCO having a controlled frequency and phase and a PRN code generator, the NCO generating a strobe that is output to the PRN code generator. The PRN code generator forms a new sequence element of +1 or -1 in response to the strobe. The apparatus also comprises a first modulator having a plurality of weight coefficients, a plurality of multipliers each multiplying one of the weight coefficients, an adder outputting a sum of the plurality of multipliers output signals, and a mixer with a quadrature output signal multiplying the adder's output by sine and cosine of a low intermediate frequency. The apparatus also includes a processor controlling the set of channels, a transceiver module to receive and / or transmit quadrature signals, and an interface connecting the output of the mixer and the transceiver module.

Embodiments include methods performed by an apparatus configured to generate output signals for transmission. Such methods include detecting a triggering condition related to a change in operational status of the apparatus and selecting one of a plurality of pre-shaping vectors based on the triggering condition and past operating conditions of the apparatus during a plurality of most recent time intervals. Each pre-shaping vector includes a plurality of values that compensate for effects of voltage variation of a power supply for the apparatus. Such methods include, during a plurality of time intervals after the triggering condition, applying the values of the selected pre-shaping vector to respective information-carrying signals, thereby generating pre-shaped information-carrying signals. Such methods include generating output signals for transmission during the plurality of subsequent time intervals, using the pre-shaped information-carrying signals. The output signals are generated by an active circuit powered by the power supply.

The invention belongs to the field of analog-to-digital converters, particularly relates to a foreground calibration system based on a pseudo-random code injection assembly line analog-to-digital converter, and aims to solve the problems that an existing calibration method of the analog-to-digital converter is not high enough in speed and too complex. The method comprises the steps that a calibration state machine controls generation of pseudo-random codes, pseudo-random code injection positions and the number of cycles; the stagei module to be calibrated receives the pseudo-random code and generates a thermometer code; the pseudo-random code changes the switching of the sampling switch differential capacitor pair; the rear-stage assembly line module receives the output of the stagei residual error amplifier as the input and outputs a digital code; the synchronized digital code is calibrated; multiplying each calibration result by the value of the pseudo-random code to obtain a product, and accumulating each product to obtain a product sum; extracting a mismatch error based on the product sum; the compensation value calculation module calculates an error compensation value; and the error compensation module compensates the output result. According to the invention, the problem of mismatch error of the capacitor can be solved.

Various techniques are provided to implement programmable linear-feedback shift register (LFSR) circuits. In one example, the LFSR circuit includes state storage elements. Each state storage element is configured to store a state signal. The LFSR circuit further includes programmable logic stage circuits each configured to selectively receive an input signal and a set of state signals, determine an output signal based at least on the set of state signals, and provide the output signal. Each programmable logic stage circuit is connected to at least one other programmable logic stage circuit. The LFSR circuit further includes pipeline elements. Each pipeline element is configured to selectively connect at least two programmable logic stage circuits. The LFSR circuit further includes sets of latency balance elements. Related systems and methods are provided.

To provide a pseudo random number generator, an analog-to-digital converter, and an electronic apparatus which can prolong the cycle of a pseudo random number with a simple circuit configuration and a small additional power consumption.SOLUTION: The pseudo random number generator includes: a main random number generation unit 10 using a first linear feedback shift register operating at a main clock CLK1; a sub random number generation unit 20 using one or more second linear feedback shift registers operating at a sub clock CLK2 having a period longer than that of the main clock CLK1; and a bit selection switch circuit 30 for replacing a part of the output bit of each register constituting the first linear feedback shift register with a replacement bit as a part of the output bit of each register constituting the second linear feedback shift register, wherein the output bit of the main random number generation unit 10 is output as a pseudo random number.SELECTED DRAWING: Figure 1

To achieve a semiconductor device which has high security against both a power analysis attack and an electromagnetic field analysis attack and supplies power to an encryption circuit.SOLUTION: A semiconductor device (101) supplies power to an encryption circuit (102) and comprises: a voltage generation unit (1) including a series regulator (5) and a shunt regulator (6); and a control unit (2) which switches the shunt regulator (6) between an on state and an off state at random.SELECTED DRAWING: Figure 1

This invention belongs to the field of electronic circuit technology, specifically relating to a true random number generation device based on a carbon-based chip, comprising: a broadband optical noise entropy source and an entropy collector. The broadband noise entropy source is used to generate a broadband chaotic noise signal. The entropy collector includes: a sample-and-hold circuit; a TIQ comparator for converting the sampling result into a digital signal output; a one-hot code generator for converting the digital signal output by the TIQ comparator into a one-hot code; and an encoder for converting the one-hot code into a binary code. In this invention, all parts of the entropy collector are designed using CNTFET technology, reducing power consumption.