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5-grade stream line structure of floating point multiplier adder integrated unit

A pipeline and floating-point multiplication technology, applied in the direction of instruments, electrical digital data processing, digital data processing components, etc., can solve problems such as increased delay, unprocessed leading zero prediction logic processing, etc.

Active Publication Date: 2008-05-07
TSINGHUA UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] (1) Unprocessed to process the one-bit left shift that may be introduced by the leading zero prediction logic
[0013] (2) The multiplication result is represented by two 48-bit partial products, which will cause a one-bit overflow error.
Its selection logic is on the critical path, increasing the delay

Method used

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  • 5-grade stream line structure of floating point multiplier adder integrated unit
  • 5-grade stream line structure of floating point multiplier adder integrated unit
  • 5-grade stream line structure of floating point multiplier adder integrated unit

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Embodiment Construction

[0117] Concrete function realization process of the present invention is as follows:

[0118] The shift alignment and inversion of A are performed in parallel with the Persian encoding and partial product compression of B×C. The addition of 1 required for complementation is accomplished using the vacant bit in the lowest bit of the 3:2 CSA carry byte. then A inv The partial product after compression with B*C is input into the 3:2CSA. A inv Indicates the output of bit-aligning the mantissa of A and inverting (if the sign bit of A is the same as the sign bit of B×C, no inversion is required). Since the partial product of B×C is only 48 bits, only A inv The lower 48 bits of the input 3: 2 CSA, the upper 55 bits are connected with the sum byte output by the CSA to obtain a 74-bit sum byte. While performing multiplication and alignment, it is judged whether the sign of A is the same as that of B×C, and the exponent difference d is calculated.

[0119] The next step is to dete...

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Abstract

The invention discloses a design of a full pipeline of a single precision floating point multiplication-add fused unit, which realizes multiplication-add operation in the form of A+B x C. the multiplication-add operation is realized in the following five pipelines: in the first stage pipeline, exponential difference is calculated and a part of the multiplication is completed; in the second stage pipeline, A and B x C are aligned according to the exponential difference, effective subtraction and complement are performed, the rest multiplication is completed, simultaneously, the exponent is divided into six states, and the calculation method of normalized shift amount in different states are different; in the third stage pipeline, the number of leading zero is pre-estimated, simultaneously the sign of the final result is synchronously pre-estimated, and finally first stage normalized shift is performed; in the fourth stage pipeline, second normalized shift is performed first, and then addition and a part of half adjust are performed; in the last stage pipeline, addition and half adjust are completed, exponential terms are amended, and third stage normalized shift is completed in the spacing of the half adjust. The invention has the advantages that high performance and high precision are realized in the condition of low hardware cost.

Description

technical field [0001] The invention relates to the design of a floating-point operation unit, which is a high-speed floating-point multiply-add fusion unit for realizing high-performance floating-point operation. Background technique [0002] Literature data show that almost 50% of floating-point multiplication instructions are followed by floating-point addition or subtraction instructions. Therefore, the floating-point multiply-add fusion operation A+B×C has become a basic operation in scientific computing and multimedia applications. Since the floating-point multiply-add fused operation occurs so frequently in applications, it has become a good choice for modern high-performance commercial processors to implement the operation with a floating-point multiply-add fused unit (referred to simply as the MAF unit). This implementation mainly has the following two advantages: (1) only one rounding is required instead of two; (2) circuit delay and hardware overhead can be reduc...

Claims

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Application Information

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IPC IPC(8): G06F7/57
Inventor 李兆麟李恭琼张轩
Owner TSINGHUA UNIV
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